Abstract: An apparatus for performing an address lookup to find a longest matching prefix for an N-bit input address in a packet data communication system that includes a memory (e.g. RAM) for storing a table containing a predefined portion of an N-bit address with an associated prefix search list containing prefix values that are candidates for the longest matching prefix. A binary search algorithm is used for selecting a specific prefix value from the prefix search list to structure the N-bit input address to form a search value. A search algorithm (e.g. a content addressable memory) is used for performing an associative search on the search value to find the longest matching prefix. The two types of memories (RAM and CAM) each provide specific functions. The RAM is used as a lookup table to provide an N/x-bit (0<x<N) binary decoding tree, and the CAM is used to provide an associative search of network addresses that are stored in logical bins that have a specific network prefix.

Abstract: A telecommunications apparatus for transporting ATM cells having either of isochronous units of payload data and asynchronous units of payload data, between receiving and transmitting ports includes a buffer for asynchronously queuing units of payload data received from the receiving ports and for subsequently transmitting the queued units of payload data in a time division multiplex data stream toward the transmitting ports. A timeslot interchanger is used to reorder a time defined sequence of isochronous units of payload data from the first data stream into a second time defined sequence of isochronous units of payload data in a second TDM data stream. An outgoing TDM data stream is assembled by transferring the first data stream into the outgoing data stream while substituting each payload occurrence of isochronous units from the second TDM data stream, into corresponding TDM locations in the outgoing data stream.

Abstract: A switch module for time switching telecommunications data includes an input circuit for selecting data samples from a time slot in an input frame of data samples. The selected data samples are arranged into groups of uniform size, each group consisting of at least two data samples. The groups of selected data samples are stored in an orderly manner, in each of as many storage entities as there are data samples in each group. Thereafter in accordance with a predefined sequence peculiar to each of the storage entities, the data samples are simultaneously read out, group by group. An output circuit selects data samples into a selected group of data samples from among each of the readouts of each of the storage entities and transmits each selected group into an output frame of data samples. Hence a sequence of the data samples appears switched in the output frame with respect to the sequence of the data samples as they were stored from the input frame.