Patents by Inventor George Franklin Frazier

George Franklin Frazier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11487561
    Abstract: According to an embodiment, a system and method are provided for constructing an accurate view of memory and events on a simulation platform. The system memory view can be used with a debug and analysis tool to provide post-processing debug, including searching forward and backward in capture time of the stored memory view to analyze the events of the simulation. The memory is constructed by capturing and storing each memory execution transaction, bus transaction, and register transaction during simulation. Changes in simulation platform hardware state may also be captured and stored in a hardware state database, including switches between process threads detected during the simulation that may update a simulator register. The captured events provide observability into the OS processes, the hardware, and the embedded software of the simulation platform.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: November 1, 2022
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Andrew Wilmot, Neeti Khullar Bhatnagar, Qizhang Chao, George Franklin Frazier
  • Patent number: 10802852
    Abstract: According to an embodiment, a system and method are provided for supporting interactive debugging of embedded software (ESW) on a simulation platform. A processor model within the simulated system will support a register and memory tracing sub-module. Simulator and emulator breakpoints will be used with the modeled objects within the tracing sub-module. For example, a simulator breakpoint may be set for the task or function that buffers the trace information so it can be written to a file. A database of register and memory values which represent the complete history of register and memory value changes during a simulation can be created from trace information and can be accessed to non-intrusively obtain any processor register or memory value during simulation. The processor register and memory values of the database can also be accessed to symbolically show the behavior of ESW concurrently with hardware behavior in the simulation.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: October 13, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Andrew R. Wilmot, Neeti Khullar Bhatnagar, Qizhang Chao, George Franklin Frazier, Yevgen Ryazanov
  • Patent number: 10650174
    Abstract: The present disclosure relates to a system and method for use in an electronic design environment. Embodiments may include receiving, using at least one processor, an electronic design and generating a unique name for each hardware state element associated with the electronic design. Embodiments may further include generating a unique name for each software state element associated with the electronic design. Embodiments may also include combining a plurality of unique names into an arbitrary expression, wherein the plurality of unique names includes at least one software state unique name and at least one hardware state unique name. Embodiments may further include evaluating the arbitrary expression at one or more discrete time points. Embodiments may also include recording an evaluated expression in an electronic design database.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: May 12, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Andrew Robert Wilmot, Rohan Kangralkar, George Franklin Frazier, Neeti Khullar Bhatnagar
  • Patent number: 7720665
    Abstract: A system for controlling reset in discrete event simulation is disclosed. The system includes a simulator configured to effect the discrete event simulation, the simulator having a plurality of shared executable files, a memory configured to store the simulator for execution, an operating system having a loading/unloading facility, and a control program configured to effect a reset operation by directing the operating system to unload the simulator from the memory and then reload the simulator into the memory using the loading/unloading facility.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: May 18, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: George Franklin Frazier, Qizhang Chao, Tuay-Ling Kathy Lang, Neeti Khullar Bhatnagar, Andrew Robert Wilmot