Patents by Inventor George G. Artnak, JR.

George G. Artnak, JR. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-tier scheme for logical storage management
    Patent number: 11068170
    Abstract: A storage device may include a controller and a memory array including a plurality of dies arranged into a plurality of channels. In some examples, the controller may be configured to define, from the memory array, a plurality of die-sets based on respective chip enable lines associated with the plurality of dies, wherein each die-set of the plurality of die-sets includes at least one die from each of the plurality of channels; define, from a selected die-set of the plurality of die-sets, a plurality of blocksets, wherein each blockset includes a block from each die of the selected die-set; receive a unit of data to be stored; and issue commands that cause the unit of data to be stored in blocks of a selected blockset of the plurality of blocksets.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: July 20, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Haining Liu, Yuriy Pavlenko, George G. Artnak, Jr.
  • Multi-Tier Scheme for Logical Storage Management
    Publication number: 20200159418
    Abstract: A storage device may include a controller and a memory array including a plurality of dies arranged into a plurality of channels. In some examples, the controller may be configured to define, from the memory array, a plurality of die-sets based on respective chip enable lines associated with the plurality of dies, wherein each die-set of the plurality of die-sets includes at least one die from each of the plurality of channels; define, from a selected die-set of the plurality of die-sets, a plurality of blocksets, wherein each blockset includes a block from each die of the selected die-set; receive a unit of data to be stored; and issue commands that cause the unit of data to be stored in blocks of a selected blockset of the plurality of blocksets.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 21, 2020
    Inventors: Haining LIU, Yuriy PAVLENKO, George G. ARTNAK, JR.
  • Multi-tier scheme for logical storage management
    Patent number: 10552055
    Abstract: A storage device may include a controller and a memory array including a plurality of dies arranged into a plurality of channels. In some examples, the controller may be configured to define, from the memory array, a plurality of die-sets based on respective chip enable lines associated with the plurality of dies, wherein each die-set of the plurality of die-sets includes at least one die from each of the plurality of channels; define, from a selected die-set of the plurality of die-sets, a plurality of blocksets, wherein each blockset includes a block from each die of the selected die-set; receive a unit of data to be stored; and issue commands that cause the unit of data to be stored in blocks of a selected blockset of the plurality of blocksets.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: February 4, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Haining Liu, Yuriy Pavlenko, George G. Artnak, Jr.
  • MULTI-TIER SCHEME FOR LOGICAL STORAGE MANAGEMENT
    Publication number: 20190227720
    Abstract: A storage device may include a controller and a memory array including a plurality of dies arranged into a plurality of channels. In some examples, the controller may be configured to define, from the memory array, a plurality of die-sets based on respective chip enable lines associated with the plurality of dies, wherein each die-set of the plurality of die-sets includes at least one die from each of the plurality of channels; define, from a selected die-set of the plurality of die-sets, a plurality of blocksets, wherein each blockset includes a block from each die of the selected die-set; receive a unit of data to be stored; and issue commands that cause the unit of data to be stored in blocks of a selected blockset of the plurality of blocksets.
    Type: Application
    Filed: March 29, 2019
    Publication date: July 25, 2019
    Inventors: Haining LIU, Yuriy PAVLENKO, George G. Artnak, JR.
  • Multi-tier scheme for logical storage management
    Patent number: 10289314
    Abstract: A storage device may include a controller and a memory array including a plurality of dies arranged into a plurality of channels. In some examples, the controller may be configured to define, from the memory array, a plurality of die-sets based on respective chip enable lines associated with the plurality of dies, wherein each die-set of the plurality of die-sets includes at least one die from each of the plurality of channels; define, from a selected die-set of the plurality of die-sets, a plurality of blocksets, wherein each blockset includes a block from each die of the selected die-set; receive a unit of data to be stored; and issue commands that cause the unit of data to be stored in blocks of a selected blockset of the plurality of blocksets.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: May 14, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Haining Liu, Yuriy Pavlenko, George G. Artnak, Jr.
  • MULTI-TIER SCHEME FOR LOGICAL STORAGE MANAGEMENT
    Publication number: 20170336990
    Abstract: A storage device may include a controller and a memory array including a plurality of dies arranged into a plurality of channels.
    Type: Application
    Filed: February 28, 2017
    Publication date: November 23, 2017
    Inventors: Haining LIU, Yuriy PAVLENKO, George G. ARTNAK, JR.
  • Multi-tier scheme for logical storage management
    Patent number: 9582201
    Abstract: A storage device may include a controller and a memory array including a plurality of dies arranged into a plurality of channels. In some examples, the controller may be configured to define, from the memory array, a plurality of die-sets based on respective chip enable lines associated with the plurality of dies, wherein each die-set of the plurality of die-sets includes at least one die from each of the plurality of channels; define, from a selected die-set of the plurality of die-sets, a plurality of blocksets, wherein each blockset includes a block from each die of the selected die-set; receive a unit of data to be stored; and issue commands that cause the unit of data to be stored in blocks of a selected blockset of the plurality of blocksets.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: February 28, 2017
    Assignee: Western Digital Technologies, Inc.
    Inventors: Haining Liu, Yuriy Pavlenko, George G. Artnak, Jr.
  • MULTI-TIER SCHEME FOR LOGICAL STORAGE MANAGEMENT
    Publication number: 20160092116
    Abstract: A storage device may include a controller and a memory array including a plurality of dies arranged into a plurality of channels.
    Type: Application
    Filed: September 26, 2014
    Publication date: March 31, 2016
    Inventors: Haining Liu, Yuriy Pavlenko, George G. Artnak, JR.