Abstract: An electrical device includes an aluminum nitride passivation layer for a mercury cadmium telluride (Hg1-xCdxTe) (MCT) semiconductor layer of the device. The AlN passivation layer may be an un-textured amorphous-to-polycrystalline film that is deposited onto the surface of the MCT in its as-grown state, or overlying the MCT after the MCT surface has been pre-treated or partially passivated, in this way fully passivating the MCT. The AlN passivation layer may have a coefficient of thermal expansion (CTE) that closely matches the CTE of the MCT layer, thereby reducing strain at an interface to the MCT. The AlN passivation layer may be formed with a neutral inherent (residual) stress, provide mechanical rigidity, and chemical resistance to protect the MCT.

Abstract: A semiconductor-based imaging device and method of manufacture. A direct bond hybridization (DBH) structure is formed on a top surface of a read out integrated circuit (ROIC). A silicon-based detector is bonded to the ROIC via the DBH structure. A non-silicon-based detector is bonded to the DBH structure located on the top of the ROIC using indium-based hybridization.

Abstract: A direct-bond hybridization (DBH) method is provided to assemble a sensor wafer device. The DBH method includes fabricating an optical element on a handle wafer and depositing first oxide with n-x thickness on the optical element where n is an expected final oxide thickness of the sensor wafer, depositing second oxide with x thickness onto a sensor wafer, executing layer transfer of the optical element by a DBH fusion bond technique to the sensor wafer whereby the first and second oxides form an oxide layer of n thickness between the optical element and the sensor wafer and removing the handle wafer.

Abstract: A semiconductor-based imaging device and method of manufacture. A direct bond hybridization (DBH) structure is formed on a top surface of a read out integrated circuit (ROIC). A silicon-based detector is bonded to the ROIC via the DBH structure. A non-silicon-based detector is bonded to the DBH structure located on the top of the ROIC using indium-based hybridization.

Abstract: An electrical device includes an aluminum nitride passivation layer for a mercury cadmium telluride (Hg1-xCdxTe) (MCT) semiconductor layer of the device. The AlN passivation layer may be an un-textured amorphous-to-polycrystalline film that is deposited onto the surface of the MCT in its as-grown state, or overlying the MCT after the MCT surface has been pre-treated or partially passivated, in this way fully passivating the MCT. The AlN passivation layer may have a coefficient of thermal expansion (CTE) that closely matches the CTE of the MCT layer, thereby reducing strain at an interface to the MCT. The AlN passivation layer may be formed with a neutral inherent (residual) stress, provide mechanical rigidity, and chemical resistance to protect the MCT.

Abstract: A semiconductor device includes a substrate with both a compressive layer and an aluminum nitride tensile layer overlying at least a portion of the substrate. The aluminum nitride tensile layer is configured to counteract the compressive layer stress in the device to thereby control an amount of substrate bow in the device. The device includes a temperature-sensitive material supported by the substrate, in which the temperature-sensitive material has a relatively low thermal degradation temperature. The aluminum nitride tensile layer is formed at a temperature below the thermal degradation temperature of the temperature-sensitive material.

Abstract: A direct-bond hybridization (DBH) method is provided to assemble a sensor wafer device. The DBH method includes fabricating an optical element on a handle wafer and depositing first oxide with n-x thickness on the optical element where n is an expected final oxide thickness of the sensor wafer, depositing second oxide with x thickness onto a sensor wafer, executing layer transfer of the optical element by a DBH fusion bond technique to the sensor wafer whereby the first and second oxides form an oxide layer of n thickness between the optical element and the sensor wafer and removing the handle wafer.

Abstract: A semiconductor-based imaging device and method of manufacture. A direct bond hybridization (DBH) structure is formed on a top surface of a read out integrated circuit (ROIC). A silicon-based detector is bonded to the ROIC via the DBH structure. A non-silicon-based detector is bonded to the DBH structure located on the top of the ROIC using indium-based hybridization.

Abstract: A method of manufacturing a wafer assembly includes forming an array of planar wafer level metal posts extending from a surface of a substrate of a first wafer. After forming the array of posts, an oxide layer is applied over the surface of the first wafer and around the array of posts, the oxide layer being applied at a temperature of below 150 degrees Celsius.

Abstract: A semiconductor device includes a substrate with both a compressive layer and an aluminum nitride tensile layer overlying at least a portion of the substrate. The aluminum nitride tensile layer is configured to counteract the compressive layer stress in the device to thereby control an amount of substrate bow in the device. The device includes a temperature-sensitive material supported by the substrate, in which the temperature-sensitive material has a relatively low thermal degradation temperature. The aluminum nitride tensile layer is formed at a temperature below the thermal degradation temperature of the temperature-sensitive material.

Abstract: A method of forming a pattern of metallic material on a substrate includes providing a plurality of void regions on a surface of the substrate. At a first temperature, a first layer of a first metallic material of a eutectic-forming pair of metallic materials is deposited on the substrate to form a conformal metallic film over the substrate and over the surfaces of the plurality of void regions. The substrate and conformal metallic film are warmed to a second temperature greater than a eutectic-liquid-formation temperature of the eutectic pair of metallic materials. At the second temperature, the second metallic material of the eutectic-forming pair of metallic materials is deposited on the conformal metallic film to initiate a eutectic-liquid-forming reaction, such that the plurality of void regions are filled with a mixture of the first and second metallic materials of the eutectic-forming pair of metallic materials.

Abstract: A method of forming a pattern of metallic material on a substrate includes providing a plurality of void regions on a surface of the substrate. At a first temperature, a first layer of a first metallic material of a eutectic-forming pair of metallic materials is deposited on the substrate to form a conformal metallic film over the substrate and over the surfaces of the plurality of void regions. The substrate and conformal metallic film are warmed to a second temperature greater than a eutectic-liquid-formation temperature of the eutectic pair of metallic materials. At the second temperature, the second metallic material of the eutectic-forming pair of metallic materials is deposited on the conformal metallic film to initiate a eutectic-liquid-forming reaction, such that the plurality of void regions are filled with a mixture of the first and second metallic materials of the eutectic-forming pair of metallic materials.

Abstract: A method of manufacturing a wafer assembly includes forming an array of planar wafer level metal posts extending from a surface of a substrate of a first wafer. After forming the array of posts, an oxide layer is applied over the surface of the first wafer and around the array of posts, the oxide layer being applied at a temperature of below 150 degrees Celsius.

Abstract: A semiconductor device has a substrate with both compressive and tensile layers deposited overlying a single major surface (face) of the device. The tensile layer may be deposited directly on the substrate of the device, with the compressive layer overlying the tensile layer. A transition material may be located between the tensile layer and the compressive layer. The transition material may be a compound including the components of one or both of the tensile layer and the compressive layer. In a specific embodiment, the tensile material may be a silicon nitride, the compressive layer may be a silicon oxide, and the transition material may be a silicon oxy-nitride, which may be formed by oxidizing the surface of the tensile silicon nitride layer. By depositing both tensile and compressive layers on the same face of the device the opposite major surface (face) is free for processing.

Abstract: A semiconductor device has a substrate with both compressive and tensile layers deposited overlying a single major surface (face) of the device. The tensile layer may be deposited directly on the substrate of the device, with the compressive layer overlying the tensile layer. A transition material may be located between the tensile layer and the compressive layer. The transition material may be a compound including the components of one or both of the tensile layer and the compressive layer. In a specific embodiment, the tensile material may be a silicon nitride, the compressive layer may be a silicon oxide, and the transition material may be a silicon oxy-nitride, which may be formed by oxidizing the surface of the tensile silicon nitride layer. By depositing both tensile and compressive layers on the same face of the device the opposite major surface (face) is free for processing.

Abstract: A method of manufacturing an array of planar wafer level metal posts includes plating an array of posts within a photoresist (PR) pattern mold on a substrate of a first wafer. Stripping the PR pattern mold from the substrate and array of posts. Applying an oxide layer, at a temperature of below 150 degrees Celsius, over a surface of the first wafer. Applying chemical-mechanical polishing (CMP) to planarize the oxide layer and the array of posts.

Abstract: A method of manufacturing an array of planar wafer level metal posts includes plating an array of posts within a photoresist (PR) pattern mold on a substrate of a first wafer. Stripping the PR pattern mold from the substrate and array of posts. Applying an oxide layer, at a temperature of below 150 degrees Celsius, over a surface of the first wafer. Applying chemical-mechanical polishing (CMP) to planarize the oxide layer and the array of posts.

Abstract: Embodiments described herein may provide an acoustic wave device, a method of fabricating an acoustic wave device, and a system incorporating an acoustic wave device. The acoustic wave device may include a transducer disposed on a substrate, with a contact coupled with the transducer. The acoustic wave device may further include a wall layer and cap that define an enclosed opening around the transducer. A via may be disposed through the cap and wall layer over the contact, and a top metal may be disposed in the via. The top metal may form a pillar in the via and a pad on the cap above the via. The pillar may provide an electrical connection between the pad and the contact. In some embodiments, the acoustic wave device may be formed as a wafer-level package on a substrate wafer.

Abstract: A SAW filter is fabricated with input and output transducers on a piezoelectric substrate and an epoxy based photo-definable acoustic absorber on the substrate for suppressing unwanted acoustic waves. The photo-definable acoustic absorber has a viscosity in a range from about 50 centistokes to 12000 centistokes and a thickness from about 10 microns to 120 microns. One acoustic absorber includes an SU-8 family member epoxy.

Abstract: Disclosed embodiments include a package having an electronic device disposed within a cavity formed by an enclosure that includes a sharp portion. The package may further include a photosensitive layer applied over the enclosure to provide a smooth portion that is adjacent to the sharp portion. Methods for manufacturing the package are also described. Other embodiments may be described and claimed.