Abstract: A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection network of the Omega gender. Programs and data are fed from the data base memory to the plurality of memory modules and from hence the programs are fed through the connection network to the array of processors (one copy of each program for each processor). Execution of the programs occur with the processors operating normally quite independently of each other in a multiprocessing fashion. For data dependent operations and other suitable operations, all processors are instructed to finish one given task or program branch before all are instructed to proceed in parallel processing fashion on the next instruction.

Abstract: In an approximate content addressable storage system data words are stored in a two dimensional storage array with each data character therein stored in a particularly associated storage row and each data word individually and sequentially character-by-character stored column-by-column. In searching the array for a particular word each storage row associated with a character in the search word is accessed in a manner biased to that character's position in the search word so that the search for all characters occurs effectively in parallel. A searched for character located in its proper position is given maximum value with decreasing value accorded to searched for characters detected one or more positions removed from the proper position in the search word. The value derived for each character is totalled with similar values derived from all other characters in the search word thus arriving at a value indicative of the approximateness of a stored word with the search word.

Abstract: A connection network is disclosed for use between a parallel array of processors and a parallel array of memory modules for establishing non-conflicting data communications paths between requested memory modules and requesting processors. The connection network includes a plurality of switching elements interposed between the processor array and the memory modules array in an Omega networking architecture. Each switching element includes a first and a second processor side port, a first and a second memory module side port, and control logic circuitry for providing data connections between the first and second processor ports and the first and second memory module ports. The control logic circuitry includes strobe logic for examining data arriving at the first and the second processor ports to indicate when the data arriving is requesting data from a requesting processor to a requested memory module.

Abstract: In a parallel processing array wherein each processor therein issues a ready signal to signify that it is ready to begin a parallel processing task and initiates the task upon receipt of an initiate signal the parallel processing array is rendered partitionable into parallel processing subarrays by a control node tree having a plurality of control nodes connected to the plurality of processors and in decreasing levels to each other in a tree-like fashion down to a single root node. Each node is controlled to function as a non-root wherein it receives a ready signal from its processor side and passes it along toward the single root node or as a root node whereupon receiving a ready signal it issues back an initiate signal toward the plurality of processors.

Abstract: An alignment network between N parallel data input ports and N parallel data outputs includes a first and a second barrel switch. The first barrel switch fed by the N parallel input ports shifts the N outputs thereof and in turn feeds the N-1 input data paths of the second barrel switch according to the relationship X=k.sup.y modulo N wherein x represents the output data path ordering of the first barrel switch, y represents the input data path ordering of the second barrel switch, and k equals a primitive root of the number N. The zero (0) ordered output data path of the first barrel switch is fed directly to the zero ordered output port. The N-1 output data paths of the second barrel switch are connected to the N output ports in the reverse ordering of the connections between the output data paths of the first barrel switch and the input data paths of the second barrel switch.

Abstract: An alignment network having N parallel data inputs includes log.sub.2 N rounded up to the nearest integer of levels, each level therein including N selection gates for providing selectively direct through data flow and incrementally shifted or transposed data flow. The selectable shift amount in each level is equal to k.sup.2.spsp.(L-1) modulo N wherein k is relatively prime to N and is a primitive root of the rank number N, and L is the number of the level. A control signal provided to each level directs whether data flow therethrough is to be direct or transposed.