Abstract: A system, method and software product achieve analysis capacity for circuit analysis tools. One or more stages of a circuit design are identified. One or more descriptions of the stages are stored. Stage results are generated by independently analyzing each stage based upon the descriptions. Stage results from analyzed stages are combined to produce a single result set for the circuit design.

Abstract: A system, method and software product determine detail of analysis in a circuit design. Pull-up driver transistors of at least one stage of the circuit design are identified. Pull-down driver transistors of the stage are identified. Configuration commands associated with control signals of the pull-up and pull-down driver transistors are processed to determine if the pull-up driver transistors and pull-down driver transistors are tied on or tied off. A determination is made whether the stage has drive fight and switching current. A detailed analysis is performed of the stage of the stage has drive fight or switching current.

Abstract: A system, method and software product processes configuration information. One or more configuration elements are identified from one or more configuration commands and associated with design elements of an electronic circuit design. Each configuration element is retrieved for at least one design element.

Abstract: A method for controlling analysis by an analysis tool of multiple instantiations of a circuit in a hierarchical circuit design is described. The method comprises providing a user-selected analysis option to the analysis tool; analyzing a first instantiation of the circuit as specified by the analysis option; and responsive to the first instantiation of the circuit passing the analysis, terminating analysis of the circuit.

Abstract: Systems, methods and software products determine activity factors of a circuit design. An activity factor is assigned to one or more node types. One or more signal nets from a netlist of the circuit design are read. The signal nets are processed to associate one of the node types with each of the signal nets. An activity factor is determined for each of the signal nets based upon node type.

Abstract: A system and method for determining unmatched design elements in a circuit. The system determines instances of a first type and a second type of the design elements that are connected to a specific node in the circuit, and stores the gate signal name for each determined said occurrence of the first type of design element in a first list. The gate signal name for each determined said occurrence of the second type of design element is than stored in a second list. A value of a design element characteristic and indicia thereof for each determined said occurrence of the first and the second types of the design elements is than stored.

Abstract: Systems, methods, and software products determine a highest level signal name in a hierarchical circuit design. A signal path is traced into a hierarchically lower level of the circuit design from a predetermined net in the circuit design to a predetermined terminal instance, while adding indicia, to an instance history list, of each subsequent instance encountered. A port instance is determined on the terminal instance associated with a selected net for which the highest level signal name is to be determined. The selected net is designated as the current net. For each stored indicia in the instance history list, the net connected to the current net in a hierarchical parent of the instance identified by the indicia is determined, to establish a next current net. If a condition exists wherein there is no connection from the current net to a hierarchically higher level instance, then the current net is established as the highest level signal name for the selected net.

Abstract: Methods, systems, software products analyze a circuit design with reduced memory utilization. Access to at least one block of the circuit design is detected. If the one block is not loaded within a circuit model of computer memory, a determination is made whether loading the one block into the circuit model would exceed a predefined maximum utilization of the computer memory. If loading the one block into the circuit model would exceed the predefined maximum utilization, one or more blocks from the circuit model are unloaded and the one block is loaded into the circuit model. If loading the one block into the circuit model would not exceed the predefined maximum utilization, the one block is loaded into the circuit model.

Abstract: Systems, methods, software products utilize fast analysis information during detailed analysis of a circuit design. One or more design blocks of the circuit design are electronically analyzed to determine fast analysis results based upon assumptions of ported signal nets of each one of the design blocks. Next, it is determined whether hierarchical signal net connectivity of block instances of the design blocks and the assumptions match. If the hierarchical signal net connectivity matches the assumptions, the fast analysis results are utilized to generate detailed analysis results. If the hierarchical signal net connectivity does not match the assumptions, the one or more blocks in the hierarchical signal net connection are electronically analyzed to generate detailed analysis results.

Abstract: A method and system for determining wire capacitance for a VLSI circuit design, comprising determining all hierarchical blocks of a portion of the design; storing, for a plurality of the blocks, indicia of the most accurate one of a plurality of wire capacitance data sources; generating a wire capacitance database with an entry for each net in at least a plurality of the blocks, using information stored in at least one of the wire capacitance data sources; generating a hierarchical connectivity model for the design; and using the hierarchical connectivity model and said wire capacitance database to determine a cumulative wire capacitance value for each HLSN in each of the blocks in a portion of the design to be analyzed.

Abstract: Systems, methods, and software products iteratively traverse a hierarchical circuit design. An initial net and an instance history that uniquely defines the initial net within the design are selected. The initial net and the instance history are appended to a list of nets to be processed. The initial net and the instance history are inserted into a set of visited nets. Each additional net connected to the initial net is visited in response to a first request from a user. The initial net and each additional net are returned in response to a second request from the user.

Abstract: A method for controlling activity of a temporary file associated with a target file to which data is to be written.

Abstract: A method for saving and automatically restoring data contained in an object in an object-oriented software environment. The method creates a ‘checkpoint object’ with a pointer to the object of interest, and a copy of the fields in the storage object that are to be saved. After a system user has completed modifications to data values in the object, the checkpoint object is destroyed, which automatically causes all of the data values in the storage object to be restored to their original states.

Abstract: Techniques are disclosed for processing events, such as errors, in an event processing computer system. For example, an event processor may receive an indication of an event (such as an error), identify a priority of the event, and determine whether an action is associated with the priority of the event. If an action is associated with the priority of the event, the action may be performed. The action may, for example, include outputting a message associated with the event to an output location. A user of the system may specify which actions the event processor is to perform for events of various priorities. For example, the user may indicate that messages should only be output for events having specified priorities. The user may specify such actions, and other parameters of the event processor, using configuration information which is distinct from the event processor.

Abstract: A method for controlling activity of a temporary file associated with a target file to which data is to be written.