Abstract: Systems, devices and methods are described including using a display engine to render first image content at a first rate, where the first image content is to be displayed by a first display at a second rate, where the first rate is larger than the second rate. The display engine may also be used to render second image content at the first rate, where the second image content is to be displayed by the second display at the second rate.

Abstract: The electric car is practically entirely covered in solar cells. Further, transparent solar cells are incorporated into the windshield and into the other windows of the car. The various features of the car give it considerable autonomy.

Abstract: A monolithic cable assembly includes a communication cable and cable connectors coupled to either end of the communication cable. The communication cable includes at least one optical communication channel. The cable connectors include a physical end connector for electrically coupling to a data device connector, optoelectronic components for converting data signals between an electrical realm and an optical realm, and a passively aligned integrated lens cover. The integrated lens cover includes at least one optical pathway for coupling optical data signals between the at least one optical communication channel and the optoelectronic components.

Abstract: A monolithic cable assembly includes a communication cable and cable connectors coupled to either end of the communication cable. The communication cable includes at least one optical communication channel. The cable connectors include a physical end connector for electrically coupling to a data device connector, optoelectronic components for converting data signals between an electrical realm and an optical realm, and a passively aligned integrated lens cover. The integrated lens cover includes at least one optical pathway for coupling optical data signals between the at least one optical communication channel and the optoelectronic components.

Abstract: The escapement includes a large plate 4 carrying a first finger 14 and a blocking member 6 carrying a second finger 11 and a locking pallet-stone 7. The first and second fingers 14 and 11 are shaped such that when the large plate 4 rotates in a first direction a, the first finger 14 drives the second 11 which moves around a first side 20 of said first finger to release the locking pallet-stone. Re-engagement occurs when the second finger 11 climbs over a vertical flank 25 of a notch 22 made in a small plate 23. When the large plate 4 rotates in a second direction b, opposite to the first, the first finger 14 drives the second finger 11 which moves around a second side 21, opposite to the first, of said first finger 14 to keep the locking pallet-stone 7 in the escapement wheel.

Abstract: The blocking member (6) or detent member of the escapement carries a follower (20) which ends in a beak (21) which cooperates with a small roller (23) comprising a notch (22). When the locking pallet-stone (7) of the blocking member releases itself from the teeth of escapement wheel (2), the beak (21) penetrates in the notch (22). The return of the pallet-stone (7) in the locking position is caused by a rising flank (25) of said notch, said rising flank being inclined such that the beak (21) is forced to follow and climb over said flank when the small roller (23) rotates. The arrangement allows the escapement to resist to shocks and consequently to omit the return spring acting on the blocking member.

Abstract: The detent escapement includes a wheel 2 fitted with teeth 3, a roller 4 fitted with an impulse pallet stone 5, a blocking member in the form of a lever 6 hinged on a pin 8. The first and second arms 9 and 10 of the lever respectively carry a locking pallet stone 7 and a first actuating finger 11. An elastic member 12 is mounted on the roller 4, said member carrying a second actuating finger 14 capable of driving the first finger 11 when the roller 4 rotates in a first direction a to actuate the blocking member 6 and to move around said first finger 11 without driving it, when the roller 4 rotates in a second direction b opposite to the first. The elastic member 12 is a spring of great length including a plurality of turns 15 wounded about a centre 16.

Abstract: A computer system is disclosed with a host bridge that arbitrates access to a system resource from a CPU via a host bus and from a set of bus agents via a peripheral bus. A separate set of priority classes are provided to the CPU and to the bus agents and programmable timers are included to tune system resource allocation between the host and processor busses.

Abstract: The present invention relates to a radio telephone watch (1) intended to be used in a mobile communication system, said watch (1) including a case (2) and a wristband (3) allowing said watch (1) to be worn on the wrist. According to the present invention, this watch further includes a casing (4; 8; 104), associated with a first strand (31) of said wristband (3), capable of receiving, in a removable manner, a SIM card (10) allowing access to said mobile communication system, an electronic module (5) arranged in said watch case (2) and allowing access to data stored in said SIM card (10), and electric connection means (6) between said SIM card (10) and said electronic module (5), integrated in said first strand (31) of the wristband (3). According to the present invention, a device (7; 9) assuring the fastening of said wristband (3) is further advantageously associated with said casing (4; 8; 104).

Abstract: A computer system is disclosed with a host bridge that arbitrates access to a system resource from a CPU via a host bus and from a set of bus agents via a peripheral bus. A separate set of priority classes are provided to the CPU and to the bus agents and programmable timers are included to tune system resource allocation between the host and processor busses.

Abstract: A computer system having an integrated bus bridge and memory controller circuit and method for enabling access to a shared memory with high bandwidth data streaming are disclosed. The integrated bus bridge and memory controller circuit performs a series of snoop ahead transactions over a first bus during access transactions to the shared memory that originate over a second bus and thereby enables high bandwidth data streaming on the second bus. The integrated bus bridge and memory controller circuit includes a peripheral write buffer that buffers write data received over the second bus and that stores a snoop done flag for the write data that indicates whether a corresponding snoop ahead transaction for the write data is complete. The integrated bus bridge and memory controller circuit further includes a peripheral read prefetch buffer that prefetches read data during read transactions over the second bus only after a corresponding snoop ahead transaction for the read data is complete.

Abstract: The present invention relates to a method and apparatus for buffering data. The apparatus stores information in a buffer. When the buffer is full, overflow data is stored in an overflow memory. As data is removed from the buffer, the overflow data is transferred from overflow memory to the buffer.

Abstract: A cache memory system having a hybrid tag architecture and a series of data lines is disclosed. The cache memory includes a cache controller and a dirty tag memory included within the cache controller. The dirty tag memory indicates the status of each data line in the cache memory. A tag memory is coupled to the cache controller and is located external to the cache controller.

Abstract: A computer system having an integrated bus bridge and memory controller circuit and method for enabling access to a shared memory with high bandwidth data streaming are disclosed. The integrated bus bridge and memory controller circuit performs a series of snoop ahead transactions over a first bus during access transactions to the shared memory that originate over a second bus and thereby enables high bandwidth data streaming on the second bus. The integrated bus bridge and memory controller circuit includes a peripheral write buffer that buffers write data received over the second bus and that stores a snoop done flag for the write data that indicates whether a corresponding snoop ahead transaction for the write data is complete. The integrated bus bridge and memory controller circuit further includes a peripheral read prefetch buffer that prefetches read data during read transactions over the second bus only after a corresponding snoop ahead transaction for the read data is complete.

Abstract: The present invention is directed to an onboard multiprotocol communications controller global serial channel ("GSC"). The GSC as disclosed and claimed herein is for use with an 8-bit microcontroller for intelligent communications with peripheral systems or components. The microcontroller and GSC are implemented on a single integrated circuit chip. The microcontroller is a derivative of the 8051 series of microcontrollers sold by INTEL Corporation. The invented GSC interface supports synchronous data link control (SDLC), carrier-sense multi-access with collision detection (CSMA/CD), and user definable (non-standard) protocols. The flexibility in defining non-standard protocols provides the ability to retrofit new products into older serial technologies, as well as the development of proprietary interconnect schemes for serial backplane environments. The GSC operates in full duplex or half-duplex mode and performs cyclic redundancy checking (CRC) for 16 or 32 bits.