Abstract: A graphics controller for high speed transmission for memory write commands. A memory controller chip includes a logic circuit coupled to a first memory and a second memory. The logic circuit is adapted to respond to a first issued command from a CPU by causing the memory controller chip to store the first command in the first memory and to begin processing the first command. If the CPU issues a second command during the time that the memory controller chip is processing the first command, the logic circuit responds by causing the memory controller chip to store the second command in the second memory.