Abstract: A process for hydrodesulfurizing an olefinic naphtha feedstock while retaining a substantial amount of the olefins, which feedstock has a T95 boiling point below 250° C. boils and contains at least 50 ppmw of organically bound sulfur and from 5% to 60% olefins, said process including (a) selective diolefin hydrogenation, under reaction conditions to convert at least 50% or 90% of the diolefins to paraffins or mono-olefins providing a pre-treated feedstock, (b) hydrodesulfurizing the pre-treated feedstock in a sulfur removal stage in the presence of hydrogen and a hydrodesulfurization catalyst, at hydrodesulfurization reaction conditions to convert at least 50% of the organically bound sulfur to hydrogen sulfide and to produce a desulfurized product stream containing from 0 ppmw to 50 ppmw organically bound sulfur, with the associated benefit of such a process providing a lower octane loss, compared to a process with a lower gas to oil ratio.

Abstract: A process for hydrodesulfurizing an olefinic naphtha feedstock while retaining a substantial amount of the olefins, which feedstock has a T95 boiling point below 250° C. boils and contains at least 50 ppmw of organically bound sulfur and from 5% to 60% olefins, said process including (a) selective diolefin hydrogenation, under reaction conditions to convert at least 50% or 90% of the diolefins to paraffins or mono-olefins providing a pre-treated feedstock, (b) hydrodesulfurizing the pre-treated feedstock in a sulfur removal stage in the presence of hydrogen and a hydrodesulfurization catalyst, at hydrodesulfurization reaction conditions to convert at least 50% of the organically bound sulfur to hydrogen sulfide and to produce a desulfurized product stream containing from 0 ppmw to 50 ppmw organically bound sulfur, with the associated benefit of such a process providing a lower octane loss, compared to a process with a lower gas to oil ratio.

Abstract: A heat exchange assembly is disclosed. In some embodiments, the heat exchange assembly includes a plurality of profiles arranged in an parallel array, each profile including a first distal portion, a central portion and a second distal portion, with a length and a width of the central portion defining a plane, the first distal portion having a curvature departing from this plane in a first direction, and the second distal portion having a curvature departing from this plane in a second direction that is opposite the first direction. An amount of piping is thermally coupled with and disposed along the length the central portion of each profile. A bracketing system statically anchors the profiles to a surface. Fluid is circulated within the piping to facilitate heat exchange between the assembly and the surrounding environment.

Abstract: A heat exchange assembly is disclosed. In some embodiments, the heat exchange assembly includes a plurality of profiles arranged in an parallel array, each profile including a first distal portion, a central portion and a second distal portion, with a length and a width of the central portion defining a plane, the first distal portion having a curvature departing from this plane in a first direction, and the second distal portion having a curvature departing from this plane in a second direction that is opposite the first direction. An amount of piping is thermally coupled with and disposed along the length the central portion of each profile. A bracketing system statically anchors the profiles to a surface. Fluid is circulated within the piping to facilitate heat exchange between the assembly and the surrounding environment.

Abstract: A device includes a first combinatorial logic stage having a first input to receive a first data value, a second input to receive a bypass value and an output to provide one of a representation of the first data value or a first predetermined value based on the bypass value. The device further includes a latch stage having a first input to receive a second data value, a second input to receive the bypass value and an output to provide one of a latched representation of the second data value or a second predetermined value based on the bypass value. The device additionally includes a second combinatorial logic stage having a first input coupled to the output of the first combinatorial logic stage, a second input coupled to the output of the latch stage, and an output.

Abstract: A method and data processing system for accessing an entry in a memory array is provided using base and offset addresses without adding the base and offset addresses. PGZO encoding is performed on the address bits of the operands. The PGZO values are evaluated using wordline generators resulting in a plurality of possible memory array entry addresses. In parallel with the PGZO operations, a carry value is generated using other bits in the operands. The result of the carry operation determines which of the possible memory array entries is selected from the memory array.

Abstract: A system (10) translates memory addresses. Processing circuitry (12) provides an effective address to a storage array (14, 16) having a plurality of stored effective addresses, each of the plurality of stored effective addresses having a corresponding pair of a lock bit and a valid bit. An output tag value and a single valid bit are provided to a comparator (18). The lock bit defines one of two predetermined classes of tasks executed by the system. The single valid bit is applicable to both of the two predetermined classes of tasks. The lock bit qualifies the clearing of the single valid bit. The comparator respectively compares the output tag value and the single valid bit with a predetermined effective address and a predetermined bit value. An output hit signal is provided when a match occurs to validate a physical address provided by a physical address array (20).

Abstract: A circuit (50) that receives dynamic signals performs both logic and latching to achieve high speed operation. The circuit has a clock that defines both an evaluation phase and a precharge phase in which the dynamic signals are evaluated during the evaluation phase. The circuit (50) functions by precharging a latch node (INT) during the evaluation phase then performing evaluation as well during the evaluation phase. The evaluation results in providing a valid logic state to the latch node. A latch circuit (54) latches this valid state during the precharge phase and holds it in this valid state during the precharge phase. This can be adapted to select which one of the dynamic signals is to be coupled and latched on the latch node (INT).

Abstract: A memory device includes a plurality of pairs of complimentary bit lines and a plurality of latch circuits. Each pair of the plurality of pairs of complimentary bit lines is coupled to a column of memory cells. Each latch circuit has an input coupled to a data line and a first output and a second output to provide complementary latched values dependent upon a value of the data line. For each latch of the plurality of latches, the first output is coupled to a first bit line of a pair of the plurality such that a value of the first bit line is continuously determined by the first output during memory device operation and the second output is coupled to a second bit line of the pair such that a value of the second bit line is continuously determined by the second output during memory device operation.

Abstract: A multistage dynamic domino circuit includes a footed dynamic domino stage, a footless dynamic domino stage, and a internal delay circuit. The footed dynamic domino stage includes a first precharge circuit, evaluation logic, and a data output coupled to the evaluation logic. The footless dynamic domino stage includes evaluation logic including a data input coupled to the data output of the footed dynamic domino stage and a second precharge circuit. The second precharge circuit includes a first precharge device including a first current terminal and a control terminal coupled to a clock line. The second precharge circuit further includes a second precharge device including a first current terminal coupled to the first current terminal of first precharge device and a control terminal. The delay circuit includes an input coupled to the clock line and an output coupled to the control terminal of the second precharge device to provide a delayed version of a clock signal provided at the input of the delay circuit.

Abstract: A memory including a NOR logic gate having an input coupled to a bitline (BL) and an input to receive the complement of the data value (DATABAR). The memory also including a NOR logic gate having an input coupled to the bitline bar (BLBAR) and an input to receive the data value (DATA). A combine stage is also included having an input coupled to an output of the NOR logic gate, an input coupled to an output of the NOR logic gate, and an output to provide a miss indicator (MISS). The miss indicator (MISS) indicates when a value on the bitline (BL) does not match the data value (DATA). The memory also comprising a plurality of bitcells coupled to the bitline (BL) and bitline bar (BLBAR), where each of the plurality of bitcells is coupled to a corresponding word line.

Abstract: A method and apparatus for performing block encoding in an asymmetrical digital subscriber line (ADSL) system uses a pipelined structure. The parity check circuit (116) contains a plurality of pipeline stages (201, 203, 205, and 207). Each stage contains an ADSL input data register (200, 202, 204, and 206) at a beginning of each stage and a carry register (208, 210, and 212) separating each stage. Each stage contains a plurality of carry circuits (214-220) which are serially coupled together by carry signals. The plurality of carry circuits (214-220) use generator polynomial root (.alpha.) processing involving serial carry propagation whereby the pipelining is implemented in the stages (201, 203, 205, and 207) in order to break the serial carry path from one long string to smaller segmented strings which are pipelined together. This pipelining is performed so that parity generation can occur at the higher frequencies required by ADSL systems.

Abstract: A transceiver (34) includes a rate adaptation buffer (74) that synchronizes a data stream received at a 4.0 kHz rate to a data stream that is transmitted at a 4.05 kHz rate. A transmit section (62) of the transceiver (34) performs rate adaptation using a single rate adaptation buffer. The transmit section (62) includes four autonomous modules which are able to access the data in the rate adaptation buffer (74) independently of one another. These four modules include a CRC-scrambler (72), a FEC encoder (76), an interleaver (78), and a constellation encoder (80). A timing controller (84) prevents contention for accesses to the rate adaptation buffer (74). In addition, each of the four modules perform their respective functions quickly enough to prevent overflow or underflow conditions in the rate adaptation buffer (74). A receive section (64) functions similarly to the transmit section (62).

Abstract: A semiconductor flash EPROM/EEPROM device which includes a command port controller for receiving command instructions from a data bus coupled to the memory device. Instruction words to a command port controller operates to instruct the device to perform read, erase, program, or verify functions and the command port controller generates necessary control signals to cause the memory to function appropriately. By utilizing the command port controller the memory device can be erased and programmed while the device is in the circuit and permits pin compatibility with the prior art EPROM and EEPROMs.

Abstract: A semiconductor flash EPROM/EEPROM device which includes a command port for receiving instruction on a data line and providing control signals to a memory for providing program and erase functions, a method to program and erase the memory. A program sequence is comprised of setting up a program command during a first write cycle, preforming a second write cycle to load address to address register and data to to a data register, programming during a program cycle and writing a program verify command during a third write cycle to verify the programmed data during a read cycle. An erase sequence is comprised of writing a setup erase command during a first write cycle, an erase command during a second write cycle providing the erasure during an erase cycle, writing the erase verify command during a third write cycle which also addresses the address of the memory and providing erase verification during a read cycle. Both the erase and program cycles provide for measured incremental erasing and programming.

Abstract: A circuit and method for verifying leakage in a flash EPROM/EEPROM memory cell which is fabricated on a silicon substrate having floating gate. A word line coupled to the control gate of the memory cell is typically at ground potential, but during a test mode a positive voltage is placed on the control gate and leakage current at the drain is measured. A good cell will typically have zero or negligible drain leakage current, however, a cell which is susceptible to being overerased will exhibit appreciable leakage current. A circuit is implemented on the chip with the memory for switching a positive voltage onto the word line during the test mode.

Abstract: A circuit and method for verifying leakage in a flash EPROM/EEPROM memory cell which is fabricated on a silicon substrate having floating gate. A word line coupled to the control gate of the memory cell is typically at ground potential, but during a test mode a positive voltage is placed on the control gate and leakage current at the drain is measured. A good cell will typically have zero or negligible drain leakage current, however, a cell which is susceptible to being overerased will exhibit appreciable leakage current. A circuit is implemented on the chip with the memory for switching a positive voltage onto the word line during the test mode.