Abstract: A velocity control system for a motor is provided wherein first counter means are reset by feedback pulses from the motor to record the feedback period. Decode means responsive to the first counter means determines whether the feedback period is long or short and the status of this is put into storage means. An up-down counter is responsive to the storage means for adjusting the motor drive pulse width and second counter means are reset by the motor feedback pulses to terminate the drive to the motor. Comparing means are responsive to the up-down counter and said second counter means for controlling the motor drive to maintain a precise motor velocity.

Abstract: A digital pulse source generates a frequency analog of a desired velocity to which a d-c motor is accelerated. The acceleration circuit comprises a circuit means for converting a frequency analog signal to a frequency dependent direct voltage and a sawtooth voltage. A comparison circuit generates a motor drive signal having a duty cycle dependent on the relative voltage levels of the direct and sawtooth voltages. The comparative duty cycle of motor drive signal for two different velocities is regulated to be proportional to the square of the ratio of the two velocities.