Patents by Inventor George J. Morales

George J. Morales has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Product design for test to enable electrical non-destructive test for measuring multi-chip interconnect defects
    Patent number: 11804413
    Abstract: A semiconductor stack, including a carrier and a semiconductor device arranged above the carrier; non-releasable interconnections electrically and mechanically connecting the semiconductor device and the carrier; a first contact on at least one of the carrier or the semiconductor device: a second contact on at least one of the carrier or the semiconductor device; an electrical connection structure electrically conductively coupling the first contact and the second contact with each other via at least one non-releasable interconnection of the non-releasable interconnections; and wherein the electrical connection structure comprises a plurality of test diode circuits integrated in at least one of the carrier and the semiconductor device, wherein each of the test diode circuits comprises one or more diodes.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: October 31, 2023
    Assignee: Intel Corporation
    Inventors: Chad Roberts, George J. Morales, Oscar Mendoza, Kartik Ramanujachar, Michael S. Chun, Anthony Zisko