Patents by Inventor George J. Scott
George J. Scott has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240117073Abstract: The present invention relates to specific binding members, particularly antibodies and fragments thereof, which bind to amplified epidermal growth factor receptor (EGFR) and to the de2-7 EGFR truncation of the EGFR. In particular, the epitope recognized by the specific binding members, particularly antibodies and fragments thereof, is enhanced or evident upon aberrant post-translational modification. These specific binding members are useful in the diagnosis and treatment of cancer. The binding members of the present invention may also be used in therapy in combination with chemotherapeutics or anti-cancer agents and/or with other antibodies or fragments thereof.Type: ApplicationFiled: April 26, 2023Publication date: April 11, 2024Inventors: Lloyd J. Old, Terrance Grant Johns, Con Panousis, Andrew M. Scott, Christoph Renner, Gerd Ritter, Achim Jungbluth, Elisabeth Stockert, Vincent Peter Collins, Webster K. Cavenee, Huei-Jen Su Huang, Antony Wilks Burgess, Edouard C. Nice, Anne Murray, George Mark
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Patent number: 9431359Abstract: A solder bump support structure and method of manufacturing thereof is provided. The solder bump support structure includes an inter-level dielectric (ILD) layer formed over a silicon substrate. The ILD layer has a plurality of conductive vias. The structure further includes a first insulation layer formed on the ILD layer. The solder bump support structure further includes a pedestal member formed on the ILD layer which includes a conductive material formed above the plurality of conductive vias in the ILD layer coaxially surrounded by a second insulation layer. The second insulation layer is thicker than the first insulation layer. The structure further includes a capping under bump metal (UBM) layer formed over, and in electrical contact with, the conductive material and formed over at least a portion of the second insulation layer of the pedestal member.Type: GrantFiled: August 8, 2013Date of Patent: August 30, 2016Assignee: International Business Machines CorporationInventors: Brian M. Erwin, Ian Melville, Ekta Misra, George J. Scott
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Patent number: 9347147Abstract: An electroplating apparatus including a reference electrode to control the potential during an electro-deposition process. The electroplating apparatus may include a bath containing a plating electrolyte and an anode present in a first portion of the bath containing the plating electrolyte. A cathode is present in a second portion of the bath containing the plating electrolyte. A reference electrode is present at a perimeter of the cathode. The electroplating apparatus also includes a control system to bias the cathode and the anode to provide a potential. A measuring system is provided in electrical communication with the reference electrode to measure the potential of the cathode. Methods of using the above described electroplating apparatus are also provided. Structures and method for electroless deposition are also provided.Type: GrantFiled: September 10, 2012Date of Patent: May 24, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles L. Arvin, Harry Cox, Hariklia Deligianni, George J. Scott
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Patent number: 9062388Abstract: An electroplating apparatus including a reference electrode to control the potential during an electro-deposition process. The electroplating apparatus may include a bath containing a plating electrolyte and an anode present in a first portion of the bath containing the plating electrolyte. A cathode is present in a second portion of the bath containing the plating electrolyte. A reference electrode is present at a perimeter of the cathode. The electroplating apparatus also includes a control system to bias the cathode and the anode to provide a potential. A measuring system is provided in electrical communication with the reference electrode to measure the potential of the cathode. Methods of using the above described electroplating apparatus are also provided. Structures and method for electroless deposition are also provided.Type: GrantFiled: August 19, 2010Date of Patent: June 23, 2015Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Harry Cox, Hariklia Deligianni, George J. Scott
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Patent number: 8778792Abstract: Solder bump connections and methods for fabricating solder bump connections. The method includes forming a layer stack containing first and second conductive layers, forming a dielectric passivation layer on a top surface of the second conductive layer, and forming a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer. The method further includes forming a conductive plug in the via opening. The solder bump connection includes first and second conductive layers comprised of different conductors, a dielectric passivation layer on a top surface of the second conductive layer, a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer, and a conductive plug in the via opening.Type: GrantFiled: February 4, 2013Date of Patent: July 15, 2014Assignee: International Business Machines CorporationInventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Ekta Misra, Christopher D. Muzzy, Wolfgang Sauter, George J. Scott
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Patent number: 8710656Abstract: An integrated circuit (IC) chip is disclosed including a plurality of metal vertical interconnect accesses (vias) in a back end of line (BEOL) layer, a redistribution layer (RDL) on the BEOL layer, the BEOL layer having a plurality of bond pads, each bond pad connected to at least one corresponding metal via through the RDL; and a solder bump connected to each bond pad, wherein each solder bump is laterally offset from the corresponding metal via connected to the bond pad towards a center of the IC chip by an offset distance, wherein the offset distance is non-uniform across the IC chip. In one embodiment, the offset distance for each solder bump is proportionate to a distance between the center of the IC chip and the center of the corresponding solder bump pad structure for that solder bump.Type: GrantFiled: July 20, 2012Date of Patent: April 29, 2014Assignee: International Business Machines CorporationInventors: Timothy H. Daubenspeck, Brian M. Erwin, Jeffrey P. Gambino, Wolfgang Sauter, George J. Scott
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Patent number: 8674506Abstract: Structures and methods to reduce maximum current density in a solder ball are disclosed. A method includes forming a contact pad in a last wiring level and forming a plurality of wires of the contact pad extending from side edges of the contact pad to respective ones of a plurality of vias. Each one of the plurality of wires has substantially the same electrical resistance.Type: GrantFiled: April 30, 2013Date of Patent: March 18, 2014Assignee: International Business Machines CorporationInventors: Raschid J. Bezama, Timothy H. Daubenspeck, Gary LaFontant, Ian D. Melville, Ekta Misra, George J. Scott, Krystyna W. Semkow, Timothy D. Sullivan, Robin A. Susko, Thomas A. Wassick, Xiaojin Wei, Steven L. Wright
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Publication number: 20140021600Abstract: An integrated circuit (IC) chip is disclosed including a plurality of metal vertical interconnect accesses (vias) in a back end of line (BEOL) layer, a redistribution layer (RDL) on the BEOL layer, the BEOL layer having a plurality of bond pads, each bond pad connected to at least one corresponding metal via through the RDL; and a solder bump connected to each bond pad, wherein each solder bump is laterally offset from the corresponding metal via connected to the bond pad towards a center of the IC chip by an offset distance, wherein the offset distance is non-uniform across the IC chip. In one embodiment, the offset distance for each solder bump is proportionate to a distance between the center of the IC chip and the center of the corresponding solder bump pad structure for that solder bump.Type: ApplicationFiled: July 20, 2012Publication date: January 23, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy H. Daubenspeck, Brian M. Erwin, Jeffrey P. Gambino, Wolfgang Sauter, George J. Scott
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Publication number: 20130320528Abstract: A solder bump support structure and method of manufacturing thereof is provided. The solder bump support structure includes an inter-level dielectric (ILD) layer formed over a silicon substrate. The ILD layer has a plurality of conductive vias. The structure further includes a first insulation layer formed on the ILD layer. The solder bump support structure further includes a pedestal member formed on the ILD layer which includes a conductive material formed above the plurality of conductive vias in the ILD layer coaxially surrounded by a second insulation layer. The second insulation layer is thicker than the first insulation layer. The structure further includes a capping under bump metal (UBM) layer formed over, and in electrical contact with, the conductive material and formed over at least a portion of the second insulation layer of the pedestal member.Type: ApplicationFiled: August 8, 2013Publication date: December 5, 2013Applicant: International Business Machines CorporationInventors: Brian M. Erwin, Ian Melville, Ekta Misra, George J. Scott
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Publication number: 20130234329Abstract: Structures and methods to reduce maximum current density in a solder ball are disclosed. A method includes forming a contact pad in a last wiring level and forming a plurality of wires of the contact pad extending from side edges of the contact pad to respective ones of a plurality of vias. Each one of the plurality of wires has substantially the same electrical resistance.Type: ApplicationFiled: April 30, 2013Publication date: September 12, 2013Applicant: Intetnational Business Machines CorporationInventors: Raschid J. BEZAMA, Timothy H. DAUBENSPECK, Gary LaFONTANT, Ian D. MELVILLE, Ekta MISRA, George J. SCOTT, Krystyna W. SEMKOW, Timothy D. SULLIVAN, Robin A. SUSKO, Thomas A. WASSICK, Xiaojin WEI, Steven L. WRIGHT
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Patent number: 8492892Abstract: Solder bump connections and methods for fabricating solder bump connections. The method includes forming a layer stack containing first and second conductive layers, forming a dielectric passivation layer on a top surface of the second conductive layer, and forming a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer. The method further includes forming a conductive plug in the via opening. The solder bump connection includes first and second conductive layers comprised of different conductors, a dielectric passivation layer on a top surface of the second conductive layer, a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer, and a conductive plug in the via opening.Type: GrantFiled: December 8, 2010Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Ekta Misra, Christopher D. Muzzy, Wolfgang Sauter, George J. Scott
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Patent number: 8446006Abstract: Structures and methods to reduce maximum current density in a solder ball are disclosed. A method includes forming a contact pad in a last wiring level and forming a plurality of wires of the contact pad extending from side edges of the contact pad to respective ones of a plurality of vias. Each one of the plurality of wires has substantially the same electrical resistance.Type: GrantFiled: December 17, 2009Date of Patent: May 21, 2013Assignee: International Business Machines CorporationInventors: Raschid J. Bezama, Timothy H. Daubenspeck, Gary LaFontant, Ian D. Melville, Ekta Misra, George J. Scott, Krystyna W. Semkow, Timothy D. Sullivan, Robin A. Susko, Thomas A. Wassick, Xiaojin Wei, Steven L. Wright
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Publication number: 20130001198Abstract: An electroplating apparatus including a reference electrode to control the potential during an electro-deposition process. The electroplating apparatus may include a bath containing a plating electrolyte and an anode present in a first portion of the bath containing the plating electrolyte. A cathode is present in a second portion of the bath containing the plating electrolyte. A reference electrode is present at a perimeter of the cathode. The electroplating apparatus also includes a control system to bias the cathode and the anode to provide a potential. A measuring system is provided in electrical communication with the reference electrode to measure the potential of the cathode. Methods of using the above described electroplating apparatus are also provided. Structures and method for electroless deposition are also provided.Type: ApplicationFiled: September 10, 2012Publication date: January 3, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles L. Arvin, Harry Cox, Hariklia Deligianni, George J. Scott
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Patent number: 8298929Abstract: Semiconductor structures, methods of manufacture and design structures are provided. The structure includes at least one offset crescent shaped solder via formed in contact with an underlying metal pad of a chip. The at least one offset crescent shaped via is offset with respect to at least one of the underlying metal pad and an underlying metal layer in direct electrical contact with an interconnect of the chip which is in electrical contact with the underlying metal layer.Type: GrantFiled: December 3, 2010Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Timothy H. Daubenspeck, Gary Lafontant, Ekta Misra, David L. Questad, George J. Scott, Krystyna W. Semkow, Timothy D. Sullivan, Thomas A. Wassick, Steven L. Wright
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Publication number: 20120146212Abstract: Solder bump connections and methods for fabricating solder bump connections. The method includes forming a layer stack containing first and second conductive layers, forming a dielectric passivation layer on a top surface of the second conductive layer, and forming a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer. The method further includes forming a conductive plug in the via opening. The solder bump connection includes first and second conductive layers comprised of different conductors, a dielectric passivation layer on a top surface of the second conductive layer, a via opening extending through the dielectric passivation layer to the top surface of the second conductive layer, and a conductive plug in the via opening.Type: ApplicationFiled: December 8, 2010Publication date: June 14, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Ekta Misra, Christopher D. Muzzy, Wolfgang Sauter, George J. Scott
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Publication number: 20120139123Abstract: Semiconductor structures, methods of manufacture and design structures are provided. The structure includes at least one offset crescent shaped solder via formed in contact with an underlying metal pad of a chip. The at least one offset crescent shaped via is offset with respect to at least one of the underlying metal pad and an underlying metal layer in direct electrical contact with an interconnect of the chip which is in electrical contact with the underlying metal layer.Type: ApplicationFiled: December 3, 2010Publication date: June 7, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy H. Daubenspeck, Gary Lafontant, Ekta Misra, David L. Questad, George J. Scott, Krystyna W. Semkow, Timothy D. Sullivan, Thomas A. Wassick, Steven L. Wright
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Publication number: 20120043301Abstract: An electroplating apparatus including a reference electrode to control the potential during an electro-deposition process. The electroplating apparatus may include a bath containing a plating electrolyte and an anode present in a first portion of the bath containing the plating electrolyte. A cathode is present in a second portion of the bath containing the plating electrolyte. A reference electrode is present at a perimeter of the cathode. The electroplating apparatus also includes a control system to bias the cathode and the anode to provide a potential. A measuring system is provided in electrical communication with the reference electrode to measure the potential of the cathode. Methods of using the above described electroplating apparatus are also provided. Structures and method for electroless deposition are also provided.Type: ApplicationFiled: August 19, 2010Publication date: February 23, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles L. Arvin, Harry Cox, Hariklia Deligianni, George J. Scott
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Publication number: 20110147922Abstract: Structures and methods to reduce maximum current density in a solder ball are disclosed. A method includes forming a contact pad in a last wiring level and forming a plurality of wires of the contact pad extending from side edges of the contact pad to respective ones of a plurality of vias. Each one of the plurality of wires has substantially the same electrical resistance.Type: ApplicationFiled: December 17, 2009Publication date: June 23, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Raschid J. BEZAMA, Timothy H. DAUBENSPECK, Gary LaFONTANT, Ian D. MELVILLE, Ekta MISRA, George J. SCOTT, Krystyna W. SEMKOW, Timothy D. SULLIVAN, Robin A. SUSKO, Thomas A. WASSICK, Xiaojin WEI, Steven L. WRIGHT