Patents by Inventor George Kotzamanis

George Kotzamanis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6121835
    Abstract: A variable time delay network (210) includes segments (270, 260) which are connected in parallel to form variable time delay network (210). Segment (270) includes a varactor diode (222) and an inductive element (223) connected in series at an anode electrode (290) of varactor (222). A cathode electrode (291) of varactor diode (222) connected to a node (220). Segment (260) includes a varactor (221) and a bypass capacitor (224) connected in series at a cathode electrode (292) of varactor (221). Cathode electrode (292) is connected at a node (225). An anode electrode (293) of varactor (221) connected to node (220). The impedance at node (220) presented to a signal that is to be time delayed remains constant at the center frequency of the signal via a bias voltage applied at node (225) while controlling and changing the time delay of the signal via a bias voltage applied at node (220).
    Type: Grant
    Filed: April 6, 2000
    Date of Patent: September 19, 2000
    Assignee: Motorola, Inc.
    Inventor: George Kotzamanis
  • Patent number: 6100757
    Abstract: A variable time delay network (210) includes segments (270, 260) which are connected in parallel to form variable time delay network (210). Segment (270) includes a varactor diode (222) and an inductive element (223) connected in series at an anode electrode (290) of varactor (222). A cathode electrode (291) of varactor diode (222) connected to a node (220). Segment (260) includes a varactor (221) and a bypass capacitor (224) connected in series at a cathode electrode (292) of varactor (221). Cathode electrode (292) is connected at a node (225). An anode electrode (293) of varactor (221) connected to node (220). The impedance at node (220) presented to a signal that is to be time delayed remains constant at the center frequency of the signal via a bias voltage applied at node (225) while controlling and changing the time delay of the signal via a bias voltage applied at node (220).
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: August 8, 2000
    Assignee: Motorola, Inc.
    Inventor: George Kotzamanis
  • Patent number: 5999046
    Abstract: A power combiner including a plurality of phasing transmission lines (122) supporting a set of amplifiers (103-105) coupled thereto, and a plurality of matching transmission lines (123-124). The set of amplifiers (103-105) have a selectable number of amplifiers between a minimum and a maximum value having gain levels between a minimum and a maximum value. Each of the matching transmission lines (123-124) is coupled to one of the phasing transmission lines (122) at one end and coupled to a common node (126) at the other end. Each of the matching transmission (123-124) lines has a characteristic impedance determined according to a function of the minimum and the maximum number of amplifiers in the set of amplifiers (103-105) and the minimum and maximum gain levels in the set of amplifiers (103-105).
    Type: Grant
    Filed: June 10, 1998
    Date of Patent: December 7, 1999
    Assignee: Motorola, Inc.
    Inventor: George Kotzamanis