Patents by Inventor George Kovall

George Kovall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230418011
    Abstract: A device includes a photonic integrated circuit (PIC) die and an electronic integrated circuit (EIC) die bonded to the PIC die. The PIC die includes a waveguide layer including a waveguide and a grating coupler configured to couple incident light into the waveguide, and a first set of dielectric layers on the waveguide layer. The EIC die includes a semiconductor substrate and a second set of dielectric layers on the semiconductor substrate. The first set of dielectric layers faces the second set of dielectric layers. The PIC die and the EIC die include a trench aligned with the grating coupler, the trench extending through the semiconductor substrate, the second set of dielectric layers, and the first set of dielectric layers to the waveguide layer such that the incident light may pass through the trench to reach the grating coupler. A multi-step dry etching process is used to form the trench.
    Type: Application
    Filed: November 9, 2021
    Publication date: December 28, 2023
    Inventors: George A. KOVALL, Takashi ORIMOTO, Gabriel MENDOZA, Vimal KAMINENI, Himani KAMINENI, Luu NGUYEN
  • Publication number: 20230123000
    Abstract: A device includes a substrate, a dielectric layer on the substrate, a waveguide within the dielectric layer, and a photodetector optically coupled to the waveguide. The photodetector is disposed above the waveguide layer and is monolithically integrated with the substrate. The photodetector is configured to operate at low temperatures, such as below about 50 K or about 20 K. In some embodiments, the monolithic photonic device includes thermal isolation structures and optical isolation structures. Techniques for manufacturing the monolithic photonic device, including the thermal isolation structures and optical isolation structures, are also described.
    Type: Application
    Filed: December 15, 2022
    Publication date: April 20, 2023
    Applicant: Psiquantum, Corp.
    Inventors: Vimal Kumar Kamineni, Matteo Staffaroni, Faraz Najafi, Ann Melnichuk, George Kovall, Yong Liang
  • Patent number: 11441941
    Abstract: A superconductor device is manufactured by depositing a barrier layer over a substrate including silicon, the barrier layer including silicon and nitrogen; depositing a seed layer for a superconductor layer over the barrier layer, the seed layer including aluminum and nitrogen; depositing the superconductor layer over the seed layer, the superconductor layer including a layer of a superconductor material, the barrier layer serving as an oxidation barrier between the layer superconductor material and the substrate; and depositing a silicon cap layer over the superconductor layer. In some embodiments, the superconductor device includes a waveguide and a metal contact at a sufficient distance from the waveguide to prevent optical coupling between the metal contact and the waveguide.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: September 13, 2022
    Assignee: PSIQUANTUM CORP.
    Inventors: Chia-Jung Chung, Faraz Najafi, George Kovall, Vitor R. Manfrinato, Vimal Kamineni, Mark Thompson, Syrus Ziai
  • Publication number: 20210239518
    Abstract: A superconductor device is manufactured by depositing a barrier layer over a substrate including silicon, the barrier layer including silicon and nitrogen; depositing a seed layer for a superconductor layer over the barrier layer, the seed layer including aluminum and nitrogen; depositing the superconductor layer over the seed layer, the superconductor layer including a layer of a superconductor material, the barrier layer serving as an oxidation barrier between the layer superconductor material and the substrate; and depositing a silicon cap layer over the superconductor layer. In some embodiments, the superconductor device includes a waveguide and a metal contact at a sufficient distance from the waveguide to prevent optical coupling between the metal contact and the waveguide.
    Type: Application
    Filed: April 15, 2021
    Publication date: August 5, 2021
    Inventors: Chia-Jung Chung, Faraz Najafi, George Kovall, Vitor R. Manfrinato, Vimal Kamineni, Mark Thompson, Syrus Ziai
  • Patent number: 11009387
    Abstract: A superconductor device according to some embodiments comprises a superconductor stack, which includes a superconductor layer and a silicon cap layer over the superconductor layer, the cap layer including amorphous silicon. The superconductor device further comprises a metal contact over a portion of the silicon cap layer and electrically-coupled to the superconductor layer. The metal contact comprises a core including a first metal, and an outer layer around the core that includes a second metal. The portion of the silicon cap layer is converted from silicon to a conductive compound including the second metal to provide low-resistance electrical coupling between the superconductor layer and the metal contact. The superconductor device further comprises a waveguide, and the first portion of the cap layer under the metal contact is at a sufficient lateral distance from the waveguide to prevent optical coupling between the metal contact and the waveguide.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: May 18, 2021
    Assignee: PSIQUANTUM CORP.
    Inventors: Chia-Jung Chung, Faraz Najafi, George Kovall, Vitor R. Manfrinato, Vimal Kamineni, Mark Thompson, Syrus Ziai
  • Publication number: 20200333179
    Abstract: A superconductor device according to some embodiments comprises a superconductor stack, which includes a superconductor layer and a silicon cap layer over the superconductor layer, the cap layer including amorphous silicon. The superconductor device further comprises a metal contact over a portion of the silicon cap layer and electrically-coupled to the superconductor layer. The metal contact comprises a core including a first metal, and an outer layer around the core that includes a second metal. The portion of the silicon cap layer is converted from silicon to a conductive compound including the second metal to provide low-resistance electrical coupling between the superconductor layer and the metal contact. The superconductor device further comprises a waveguide, and the first portion of the cap layer under the metal contact is at a sufficient lateral distance from the waveguide to prevent optical coupling between the metal contact and the waveguide.
    Type: Application
    Filed: April 15, 2020
    Publication date: October 22, 2020
    Inventors: Chia-Jung Chung, Faraz Najafi, George Kovall, Vitor R. Manfrinato, Vimal Kamineni, Mark Thompson, Syrus Ziai
  • Patent number: 7910429
    Abstract: Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g.
    Type: Grant
    Filed: April 7, 2004
    Date of Patent: March 22, 2011
    Assignee: ProMOS Technologies, Inc.
    Inventors: Zhong Dong, Chuck Jang, Ching-Hwa Chen, Chunchieh Huang, Jin-Ho Kim, Vei-Han Chan, Chung Wai Leung, Chia-Shun Hsiao, George Kovall, Steven Ming Yang
  • Publication number: 20090057266
    Abstract: In one embodiment, a method includes providing a plasma etch reactor including a vacuum chamber and an electrode disposed inside of the chamber, and providing a stack to be etched over the electrode, the stack including a patterned photoresist over a dielectric layer. The method further includes providing a chamber pressure between about 75 mT and about 150 mT, flowing gases including CF4 and CHF3 at a ratio between about 2.5:1 and about 5.0:1 into the chamber, applying RF power to the electrode between about 300 W and about 500 W to form a plasma from the gases, and etching the dielectric layer with the plasma through the patterned photoresist.
    Type: Application
    Filed: August 27, 2007
    Publication date: March 5, 2009
    Inventors: Eda Tuncel, George Kovall
  • Patent number: 7297628
    Abstract: Inwardly-tapered openings are created in an Anti-Reflection Coating layer (ARC layer) provided beneath a patterned photoresist layer. The smaller, bottom width dimensions of the inwardly-tapered openings are used for defining further openings in an interlayer dielectric region (ILD) provided beneath the ARC layer. In one embodiment, the ILD separates an active layers set of an integrated circuit from its first major interconnect layer. Further in one embodiment, a taper-inducing etch recipe is used to create the inwardly-tapered ARC openings, where the etch recipe uses a mixture of CF4 and CHF3 and where the CF4/CHF3 volumetric inflow ratio is substantially less than 5 to 1, and more preferably closer to 1 to 1.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: November 20, 2007
    Assignee: Promos Technologies, Inc.
    Inventors: Chunyuan Chao, Kuei-Chang Tsai, George A. Kovall
  • Publication number: 20050227437
    Abstract: Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g.
    Type: Application
    Filed: April 7, 2004
    Publication date: October 13, 2005
    Inventors: Zhong Dong, Chuck Jang, Ching-Hwa Chen, Chunchieh Huang, Jin-Ho Kim, Vei-Han Chan, Chung Leung, Chia-Shun Hsiao, George Kovall, Steven Yang
  • Publication number: 20050106882
    Abstract: Inwardly-tapered openings are created in an Anti-Reflection Coating layer (ARC layer) provided beneath a patterned photoresist layer. The smaller, bottom width dimensions of the inwardly-tapered openings are used for defining further openings in an interlayer dielectric region (ILD) provided beneath the ARC layer. In one embodiment, the ILD separates an active layers set of an integrated circuit from its first major interconnect layer. Further in one embodiment, a taper-inducing etch recipe is used to create the inwardly-tapered ARC openings, where the etch recipe uses a mixture of CF4 and CHF3 and where the CF4/CHF3 volumetric inflow ratio is substantially less than 5 to 1, and more preferably closer to 1 to 1.
    Type: Application
    Filed: November 19, 2003
    Publication date: May 19, 2005
    Inventors: Chunyuan Chao, Kuei-Chang Tsai, George Kovall
  • Publication number: 20050048788
    Abstract: Significant amounts of micromasking residue have been observed at the interface between a Ti-containing ARC layer and a PE-TEOS hardmask after the hardmask has been etched and prior to the use of the etched hardmask for transferring a pattern to an underlying metal layer (e.g., aluminum). The micromasking residue can interfere with proper etching of the underlying metal layer such as by creating undesirable short circuits between metal interconnect lines. Methods are disclosed for removing and/or preventing the formation of the micromasking residue. A removing method includes the use of a relatively low average-mass physical bombardment agent in combination with a small-diameter, chemically-reactive agent for dislodging micromasking nodules by weakening their base anchors and breaking them away without causing excessive damage to underlying layers. In one embodiment, the base anchors are rich in titanium content while the micromasking nodule bodies contain titanium oxide.
    Type: Application
    Filed: August 26, 2003
    Publication date: March 3, 2005
    Inventors: Woody Tang, George Kovall, Yi Ding
  • Publication number: 20040192059
    Abstract: A method of plasma etching a metal stack on a semiconductor wafer is presented. The metal stack includes an aluminum layer overlaid with a titanium-containing anti-reflective coating (ARC) layer. The method includes flowing a fluorine-containing species (e.g., SF6) and a chlorine-containing species (e.g., BCl3 and Cl2) into a plasma etch chamber while etching the titanium-containing ARC layer.
    Type: Application
    Filed: March 28, 2003
    Publication date: September 30, 2004
    Applicant: Mosel Vitelic, Inc.
    Inventors: Woody K. Sattayapiwat Tang, George A. Kovall