Patents by Inventor George L. Geannopoulos
George L. Geannopoulos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10033402Abstract: Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.Type: GrantFiled: September 14, 2016Date of Patent: July 24, 2018Assignee: Intel CorporationInventors: Takao Oshita, George L. Geannopoulos, David E. Duarte, J. Keith Hodgson, James S. Ayers, Avner Kornfeld, Jonathan P. Douglas
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Patent number: 9921592Abstract: Described is an apparatus which comprises: a bandgap core to provide a control signal; and an output stage coupled to the bandgap core, the output stage to receive the control signal and to provide a low impedance output at an output node.Type: GrantFiled: September 9, 2013Date of Patent: March 20, 2018Assignee: INTEL CORPORATIONInventors: Joseph Shor, George L. Geannopoulos, Fabrice Paillet, Lan D. Vu, Oleg Dadashev
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Publication number: 20170005670Abstract: Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.Type: ApplicationFiled: September 14, 2016Publication date: January 5, 2017Inventors: Takao Oshita, George L. Geannopoulos, David E. Duarte, J. Keith Hodgson, James S. Ayers, Avner Kornfeld, Jonathan P. Douglas
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Patent number: 9520895Abstract: Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.Type: GrantFiled: May 6, 2015Date of Patent: December 13, 2016Assignee: Intel CorporationInventors: Takao Oshita, George L. Geannopoulos, David E. Duarte, J Keith Hodgson, James S. Ayers, Avner Kornfeld, Jonathan P. Douglas
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Publication number: 20160246315Abstract: Described is an apparatus which comprises: a bandgap core to provide a control signal; and an output stage coupled to the bandgap core, the output stage to receive the control signal and to provide a low impedance output at an output node.Type: ApplicationFiled: September 9, 2013Publication date: August 25, 2016Inventors: Joseph SHOR, George L. GEANNOPOULOS, Fabrice PAILLET, Lan D. VU, Oleg DADASHEV
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Publication number: 20160233879Abstract: Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.Type: ApplicationFiled: May 6, 2015Publication date: August 11, 2016Inventors: Takao Oshita, George L. Geannopoulos, David E. Duarte, J. Keith Hodgson, James S. Ayers, Avner Kornfeld, Jonathan P. Douglas
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Patent number: 9213382Abstract: Described is a linear voltage regulator circuit comprising a first voltage regulator comprising a first source follower having a first node to provide a first power supply, and a second node different from the first node; and a second voltage regulator comprising a second source follower having a first node to provide a second power supply, and a second node different from the first node, wherein the second nodes of the first and second voltage regulators are electrically shorted.Type: GrantFiled: September 12, 2012Date of Patent: December 15, 2015Assignee: Intel CorporationInventors: Fabrice Paillet, Joseph Shor, George L. Geannopoulos, Hong Yun Tan
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Patent number: 9065470Abstract: Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.Type: GrantFiled: December 19, 2012Date of Patent: June 23, 2015Assignee: Intel CorporationInventors: Takao Oshita, George L. Geannopoulos, David E. Duarte, J Keith Hodgson, James S. Ayers, Avner Kornfeld, Jonathan P. Douglas
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Patent number: 9046552Abstract: Described is an apparatus to trim on-die passive components. The apparatus comprises: a resistor-capacitor (RC) dominated oscillator independent of first order transistor speed dependency, wherein the RC dominated oscillator including one or more resistors and capacitors with programmable resistance and capacitance, and wherein the RC dominated oscillator to generate an output signal having a frequency depending substantially on values of the programmable resistance and capacitance; and a trim-able resistor or capacitor operable to be trimmed, for compensating process variations, according to a program code associated with the programmable resistance and capacitance of the RC dominated oscillator.Type: GrantFiled: June 27, 2013Date of Patent: June 2, 2015Assignee: Intel CorporationInventors: Fabrice Paillet, Gerhard Schrom, Alexander Lyakhov, George L. Geannopoulos, Ravi Sankar Vunnam, J. Keith Hodgson
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Publication number: 20140266486Abstract: Described is an apparatus to trim on-die passive components. The apparatus comprises: a resistor-capacitor (RC) dominated oscillator independent of first order transistor speed dependency, wherein the RC dominated oscillator including one or more resistors and capacitors with programmable resistance and capacitance, and wherein the RC dominated oscillator to generate an output signal having a frequency depending substantially on values of the programmable resistance and capacitance; and a trim-able resistor or capacitor operable to be trimmed, for compensating process variations, according to a program code associated with the programmable resistance and capacitance of the RC dominated oscillator.Type: ApplicationFiled: June 27, 2013Publication date: September 18, 2014Inventors: Fabrice PAILLET, Gerhard SCHROM, Alexander LYAKHOV, George L. GEANNOPOULOS, Ravi Sankar VUNNAM, J. Keith HODGSON
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Publication number: 20140167991Abstract: Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.Type: ApplicationFiled: December 19, 2012Publication date: June 19, 2014Inventors: Takao Oshita, George L. Geannopoulos, David E. Duarte, J. Keith Hodgson, James S. Ayers, Avner Kornfeld, Jonathan P. Douglas
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Publication number: 20140070876Abstract: Described is a linear voltage regulator circuit comprising a first voltage regulator comprising a first source follower having a first node to provide a first power supply, and a second node different from the first node; and a second voltage regulator comprising a second source follower having a first node to provide a second power supply, and a second node different from the first node, wherein the second nodes of the first and second voltage regulators are electrically shorted.Type: ApplicationFiled: September 12, 2012Publication date: March 13, 2014Inventors: Fabrice Paillet, Joseph Shor, George L. Geannopoulos, Hong Yun Tan
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Patent number: 6727597Abstract: An integrated circuit having a first plurality of wire bond pads located along a horizontal axis, a second plurality of wire bond pads located along a vertical axis, and a plurality of C4 pads arranged in a grid array wherein each grid is defined by the intersection of one of the first wire bond pads and one of the second wire bond pads.Type: GrantFiled: December 27, 2001Date of Patent: April 27, 2004Assignee: Intel CorporationInventors: Gregory F. Taylor, George L. Geannopoulos
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Publication number: 20020109240Abstract: An integrated circuit having a first plurality of wire bond pads located along a horizontal axis, a second plurality of wire bond pads located along a vertical axis, and a plurality of C4 pads arranged in a grid array wherein each grid is defined by the intersection of one of the first wire bond pads and one of the second wire bond pads.Type: ApplicationFiled: December 27, 2001Publication date: August 15, 2002Inventors: Gregory F. Taylor, George L. Geannopoulos
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Patent number: 6410990Abstract: An integrated circuit having a first plurality of wire bond pads located along a horizontal axis, a second plurality of wire bond pads located along a vertical axis, and a plurality of C4 pads arranged in a grid array wherein each grid is defined by the intersection of one of the first wire bond pads and one of the second wire bond pads.Type: GrantFiled: December 12, 1997Date of Patent: June 25, 2002Assignee: Intel CorporationInventors: Gregory F. Taylor, George L. Geannopoulos
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Publication number: 20010013663Abstract: An integrated circuit having a first plurality of wire bond pads located along a horizontal axis, a second plurality of wire bond pads located along a vertical axis, and a plurality of C4 pads arranged in a grid array wherein each grid is defined by the intersection of one of the first wire bond pads and one of the second wire bond pads.Type: ApplicationFiled: December 12, 1997Publication date: August 16, 2001Inventors: GREGORY F. TAYLOR, GEORGE L. GEANNOPOULOS
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Patent number: 6075285Abstract: An apparatus that efficiently delivers electrical power and lowers the inductance to an integrated circuit. In one embodiment, the present invention includes an apparatus for delivering electrical power to an integrated circuit comprising two planes, substantially parallel to one another, having many ground and power traces. The ground and power traces of the separate planes are connected together and connected to the integrated circuit, thereby providing power to the integrated circuit. In each individual plane, the ground and power traces are substantially parallel to each other, one array of traces in one plane substantially perpendicular to another array of traces in another plane. The apparatus being electrically coupled to a printed circuit board having at least one decoupling capacitor with first and second electrodes coupled to at least two of the ground and power connections, respectively, of the integrated circuit through the printed circuit board, and the first and second ground and power planes.Type: GrantFiled: December 15, 1997Date of Patent: June 13, 2000Assignee: Intel CorporationInventors: Gregory F. Taylor, George L. Geannopoulos, Larry E. Mosley
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Patent number: 5654656Abstract: The reset circuit includes a first current mirror coupled to a first terminal of a power supply. A second current mirror is coupled to a second terminal of the power supply. First and second switches couple the first current mirror to the second current mirror. A threshold detector provides a first signal when a current differential between the first and second current mirrors exceeds a predetermined threshold. A first shunt shunts the first current mirror to the first terminal. A second shunt shunts the second current mirror to the second terminal. Buffering circuitry controls the first and second switches and the first and second shunts in response to the first signal. The buffering circuitry further provides a buffered reset signal from the first signal. The buffered reset signal transitions from a first level to a second level in response to the first signal. The switches and shunts reduce the biases on the threshold detector and current mirrors.Type: GrantFiled: March 18, 1996Date of Patent: August 5, 1997Assignee: Intel CorporationInventor: George L. Geannopoulos
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Patent number: 4684826Abstract: A circuit constructed in accordance with this invention includes means for asynchronously forcing a flip-flop (70) or a register to a programmable logical state in response to an initialization input signal (I). In one embodiment, a D-type flip-flop (70) is provided having data input terminal (71), a clock input terminal (77), a data output terminal (103), an initialization input terminal (41), and a programming input terminal (11). When an initialization input signal I is received, a predefined output signal is immediately placed on the data output terminal (103). The predefined output signal is defined by the status of a fuse (13), which is opened, if desired, via the programming input terminal (11). When an initialization input signal is not received, the flip-flop (70) operates as a normal D-type flip-flop.Type: GrantFiled: July 20, 1984Date of Patent: August 4, 1987Assignee: Monolithic Memories, Inc.Inventors: Michael G. France, George L. Geannopoulos, Robert J. Bosnyak, Steve Y. Chan