Abstract: In one embodiment, a method for parallel routing of a circuit design is provided. Placement of a netlist of the circuit design is determined for a target device. A plurality of regions of the target device is defined. Each region of the plurality of regions is assigned to a respective set of processors, each set including at least one processor. Global routing of nets of the netlist on the target device is performed. The global routing of each net restricts the net to one or more possible routes through a corresponding subset of the plurality of regions. Local routing of the netlist is concurrently performed within the plurality of regions using the respective sets of processors. Within each region, the local routing of the netlist is performed exclusively by the respective set of one or more processors.

Abstract: Method, apparatus, and computer readable medium for modeling an integrated circuit in a computer aided design system (CAD) are described. In some examples, a device model of the integrated circuit is generated in at least one first computer file, the device model having a component hierarchy. A common delay identifier is defined for component instances in the component hierarchy of the device model. A value model is generated for the device model in at least one second computer file. Delay values are defined for the common delay identifier in the value model, at least a portion of the delay values being qualified based on location in the component hierarchy of at least one of the component instances.

Abstract: Method and apparatus for implementing a pre-implemented circuit design for a programmable logic device is described. In one example, a definition of the pre-implemented circuit design is obtained (504). The definition includes a first physical implementation and a first logical implementation. A second logical implementation is produced (506) for an instance of the pre-implemented circuit design using the first logical implementation. A second physical implementation is produced (510, 512) for then instance of the pre-implemented circuit design using the first physical implementation.