Abstract: A monitoring circuit for a CES element is provided. The circuit includes a control circuit and an output circuit. The control circuit is configured to vary a control signal provided to the CES element. The control signal may be varied for determining an impedance state of the CES element. The output circuit provided an output signal in dependence on the determined impedance state of the CES element.

Abstract: A monitoring circuit for a CES element is provided. The circuit includes a control circuit and an output circuit. The control circuit is configured to vary a control signal provided to the CES element. The control signal may be varied for determining an impedance state of the CES element. The output circuit provided an output signal in dependence on the determined impedance state of the CES element.

Abstract: A monitoring circuit for a CES element is provided. The circuit includes a control circuit and an output circuit. The control circuit is configured to vary a control signal provided to the CES element. The control signal may be varied for determining an impedance state of the CES element. The output circuit provided an output signal in dependence on the determined impedance state of the CES element.

Abstract: Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12. The column select signal is boosted to a lower than normal level when a column is unselected and to higher than a normal level when a column is selected. Voltage boost circuitry, such as charge pumps 20, 22 are employed within the column select circuitry 12 to achieve these boosted levels for the columns select signal.

Abstract: Various implementations described herein may refer to and may be directed to using port modes with memory. In one implementation, a memory device may include access control circuitry used to selectively activate one of a plurality of first word-lines based on first address signals from a first access port, and used to selectively activate one of a plurality of second word-lines based on assigned address signals. The access control circuitry may include address selection circuitry configured to select the assigned address signals based on a port mode signal, where the address selection circuitry selects the first address signals as the assigned address signals when the port mode signal indicates a single port mode, and where the address selection circuitry selects second address signals from a second access port as the assigned address signals when the port mode signal indicates a dual port mode.

Abstract: A monitoring circuit for a CES element is provided. The circuit includes a control circuit and an output circuit. The control circuit is configured to vary a control signal provided to the CES element. The control signal may be varied for determining an impedance state of the CES element. The output circuit provided an output signal in dependence on the determined impedance state of the CES element.

Abstract: An integrated circuit 2 includes a transistor 26 which has a normal switching speed arising during normal operations of that transistor that apply electrical signals within normal ranges. If it is desired to change the speed of operation of the transistor, then speed tuning circuitry 12 applies a tuning electrical signal with a tuning characteristic outside of the normal range of characteristics to the transistor concerned. The tuning electrical signal induces a change in at least one of the physical properties of that transistor such that when it resumes its modified normal operations the switching speed of that transistor will have changed. The tuning electrical signal may be a voltage (or current) outside of the normal range of voltages applied to the gate of a transistor so as to induce a permanent increase in the threshold of that transistor and so slow its speed of switching. Temperature of a transistor may also be controlled to induce a permanent change in performance/speed.

Abstract: Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12. The column select signal is boosted to a lower than normal level when a column is unselected and to higher than a normal level when a column is selected. Voltage boost circuitry, such as charge pumps 20, 22 are employed within the column select circuitry 12 to achieve these boosted levels for the columns select signal.

Abstract: Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12. The column select signal is boosted to a lower than normal level when a column is unselected and to higher than a normal level when a column is selected. Voltage boost circuitry, such as charge pumps 20, 22 are employed within the column select circuitry 12 to achieve these boosted levels for the columns select signal.

Abstract: Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12. The column select signal is boosted to a lower than normal level when a column is unselected and to higher than a normal level when a column is selected. Voltage boost circuitry, such as charge pumps 20, 22 are employed within the column select circuitry 12 to achieve these boosted levels for the columns select signal.

Abstract: An integrated circuit 2 includes a transistor 26 Which has a normal switching speed arising during normal operations of that transistor that apply electrical signals within normal ranges. If it is desired to change the speed of operation of the transistor, then speed tuning circuitry 12 applies a tuning electrical signal with a tuning characteristic outside of the normal range of characteristics to the transistor concerned. The tuning electrical signal induces a change in at least one of the physical properties of that transistor such that when it resumes its modified normal operations the switching speed of that transistor will have changed. The tuning electrical signal may be a voltage (or current) outside of the normal range of voltages applied to the gate of a transistor so as to induce a permanent increase in the threshold of that transistor and so slow its speed of switching. Temperature of a transistor may also be controlled to induce a permanent change in performance/speed.

Abstract: An apparatus includes a first processor that accesses memory according to a first clock frequency, a second processor that accesses memory according to a second clock frequency, and a memory device is configurable to selectively operate according to the first clock frequency or the second clock frequency. A memory controller enables dynamic configuration of organization of the memory device to allow a first portion of the memory device to be accessed by the first processor according to the first clock frequency and a second portion of the memory device to be accessed by the second processor according to the second clock frequency.

Abstract: An apparatus includes a first processor that accesses memory according to a first clock frequency, a second processor that accesses memory according to a second clock frequency, and a memory device is configurable to selectively operate according to the first clock frequency or the second clock frequency. A memory controller enables dynamic configuration of organization of the memory device to allow a first portion of the memory device to be accessed by the first processor according to the first clock frequency and a second portion of the memory device to be accessed by the second processor according to the second clock frequency.

Abstract: A de-coupled memory access system including a memory access control circuit configured to generate first and second independent, de-coupled time references. The memory access control circuit includes a read initiate circuit responsive to the first time reference and a read signal for generating a read enable signal, and a write initiate circuit responsive to the second time reference and a write signal for generating a write enable signal independent of the read enable signal for providing independent, de-coupled write access to a memory array.