Abstract: Described is a multiple-camera system and process for detecting, tracking, and re-verifying agents within a materials handling facility. In one implementation, a plurality of feature vectors may be generated for an agent and maintained as an agent model representative of the agent. When the object being tracked as the agent is to be re-verified, feature vectors representative of the object are generated and stored as a probe agent model. Feature vectors of the probe agent model are compared with corresponding feature vectors of candidate agent models for agents located in the materials handling facility. Based on the similarity scores, the agent may be re-verified, it may be determined that identifiers used for objects tracked as representative of the agents have been flipped, and/or to determine that tracking of the object representing the agent has been dropped.

Abstract: An identification system includes one or more infrared light sources and a camera that acquires images of a user's palm. For example, at a first time, one or more first images may be acquired by the camera using infrared light with a first polarization that represent external characteristics of the user's palm. At a second time, one or more second images may be acquired using infrared light with a second polarization that represent internal characteristics of the user's palm. These images are processed to determine a first set of feature vectors and a second set of feature vectors. A current signature may be determined using the first set of feature vectors and the second set of feature vectors. In addition, a user may be identified based on a comparison of the current signature and previously stored reference signatures that are associated with candidate user identifiers.

Abstract: Described are systems and methods for training machine learning models of an ensemble of models that are de-correlated. For example, two or more machine learning models may be concurrently trained (e.g., co-trained) while adding a decorrelation component to one or both models that decreases the pairwise correlation between the outputs of the models. Unlike traditional approaches, in accordance with the disclosed implementations, only the negative results need to be decorrelated.

Abstract: Disclosed are systems and method for training an ensemble of machine learning models with a focus on feature engineering. For example, the training of the models encourages each machine learning model of the ensemble to rely on a different set of input features from the training data samples used to train the machine learning models of the ensemble. However, instead of telling each model explicitly which features to learn, in accordance with the disclosed implementations, ML models of the ensemble may be trained sequentially, with each new model trained to disregard input features learned by previously trained ML models of the ensemble and learn based on other features included in the training data samples.

Abstract: Described is a multiple-camera system and process for detecting, tracking, and re-verifying agents within a materials handling facility. In one implementation, a plurality of feature vectors may be generated for an agent and maintained as an agent model representative of the agent. When the object being tracked as the agent is to be re-verified, feature vectors representative of the object are generated and stored as a probe agent model. Feature vectors of the probe agent model are compared with corresponding feature vectors of candidate agent models for agents located in the materials handling facility. Based on the similarity scores, the agent may be re-verified, it may be determined that identifiers used for objects tracked as representative of the agents have been flipped, and/or to determine that tracking of the object representing the agent has been dropped.

Abstract: A method for handling load faults in an out-of-order processor is described. The method includes detecting, by a memory ordering buffer of the out-of-order processor, a load fault corresponding to a load instruction that was executed out-of-order by the out-of-order processor; determining, by the memory ordering buffer, whether instant reclamation is available for resolving the load fault of the load instruction; and performing, in response to determining that instant reclamation is available for resolving the load fault of the load instruction, instant reclamation to re-fetch the load instruction for execution prior to attempting to retire the load instruction.

Abstract: A non-contact biometric identification system includes a hand scanner that generates images of a user's palm. Images are acquired using light of a first polarization at a first time that show surface characteristics such as wrinkles in the palm while images acquired using light of a second polarization at a second time show deeper characteristics such as veins. Within the images, the palm is identified and subdivided into sub-images. The sub-images are subsequently processed to determine feature vectors present in each sub-image. A current signature is determined using the feature vectors. A user may be identified based on a comparison of the current signature with a previously stored reference signature that is associated with a user identifier.

Abstract: A non-contact biometric identification system includes a hand scanner that generates images of a user's palm. Images are acquired using light of a first polarization at a first time show surface characteristics such as wrinkles in the palm while images acquired using light of a second polarization at a second time show deeper characteristics such as veins. Within the images, the palm is identified and subdivided into sub-images. The sub-images are subsequently processed to determine feature vectors present in each sub-image. A current signature is determined using the feature vectors. A user may be identified based on a comparison of the current signature with a previously stored reference signature that is associated with a user identifier.

Abstract: A method for handling load faults in an out-of-order processor is described. The method includes detecting, by a memory ordering buffer of the out-of-order processor, a load fault corresponding to a load instruction that was executed out-of-order by the out-of-order processor; determining, by the memory ordering buffer, whether instant reclamation is available for resolving the load fault of the load instruction; and performing, in response to determining that instant reclamation is available for resolving the load fault of the load instruction, instant reclamation to re-fetch the load instruction for execution prior to attempting to retire the load instruction.

Abstract: A method for handling load faults in an out-of-order processor is described. The method includes detecting, by a memory ordering buffer of the out-of-order processor, a load fault corresponding to a load instruction that was executed out-of-order by the out-of-order processor; determining, by the memory ordering buffer, whether instant reclamation is available for resolving the load fault of the load instruction; and performing, in response to determining that instant reclamation is available for resolving the load fault of the load instruction, instant reclamation to re-fetch the load instruction for execution prior to attempting to retire the load instruction.

Abstract: A method for handling load faults in an out-of-order processor is described. The method includes detecting, by a memory ordering buffer of the out-of-order processor, a load fault corresponding to a load instruction that was executed out-of-order by the out-of-order processor; determining, by the memory ordering buffer, whether instant reclamation is available for resolving the load fault of the load instruction; and performing, in response to determining that instant reclamation is available for resolving the load fault of the load instruction, instant reclamation to re-fetch the load instruction for execution prior to attempting to retire the load instruction.

Abstract: A processor includes a core, a memory subsystem, a predictor module, and a memory rename module. The predictor module may include a first logic to identify a dependency between a store instruction and a load instruction, and a second logic to assign a memory renaming (MRN) register to the store instruction and the load instruction based on the identified dependency. Further, the memory rename module may include a third logic to copy, based on the assigned MRN register, information in a first logical register associated with the store instruction directly to a second logical register associated with the load instruction.

Abstract: In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, a restriction logic to receive a restriction command and to reduce delivery of the first clock signal to at least one of the plurality of units. The restriction logic may cause the first clock signal to be distributed to the plurality of units at a lower frequency than a frequency of the first clock signal. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor has a core to execute instructions which includes a first cache memory, a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, and a core activity monitor logic to monitor activity of the core and, responsive to a miss in the first cache memory, to send a first restriction command to cause the clock generation logic to reduce delivery of the first clock signal to at least one of the units to a first frequency less than a frequency of the first clock signal. Other embodiments are described and claimed.

Abstract: A processor includes a core, a memory subsystem, a predictor module, and a memory rename module. The predictor module may include a first logic to identify a dependency between a store instruction and a load instruction, and a second logic to assign a memory renaming (MRN) register to the store instruction and the load instruction based on the identified dependency. Further, the memory rename module may include a third logic to copy, based on the assigned MRN register, information in a first logical register associated with the store instruction directly to a second logical register associated with the load instruction.

Abstract: In an embodiment, a processor has a core to execute instructions which includes a first cache memory, a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, and a core activity monitor logic to monitor activity of the core and, responsive to a miss in the first cache memory, to send a first restriction command to cause the clock generation logic to reduce delivery of the first clock signal to at least one of the units to a first frequency less than a frequency of the first clock signal. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, a restriction logic to receive a restriction command and to reduce delivery of the first clock signal to at least one of the plurality of units. The restriction logic may cause the first clock signal to be distributed to the plurality of units at a lower frequency than a frequency of the first clock signal. Other embodiments are described and claimed.

Abstract: An apparatus and method are described for performing history-based prefetching. For example a method according to one embodiment comprises: determining if a previous access signature exists in memory for a memory page associated with a current stream; if the previous access signature exists, reading the previous access signature from memory; and issuing prefetch operations using the previous access signature.

Abstract: A method includes combining at least two 3-D models, given the positions of the models and constraint areas of the models that should not be changed by the combination. The combining includes generating a weighted graph representation of the models at least in a transition volume and including at least a portion of the constraint areas and finding a minimum cut which separates the weighted graph into two cut graphs representing cut versions of the models.