Patents by Inventor George M. Braceras
George M. Braceras has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10978143Abstract: A structure includes a multi-port memory including a multiple transistor bitcell single ended read port and a write port, a read circuit which is connected to a multiple transistor bitcell circuit and is also configured to evaluate the multiple transistor bitcell single ended read port, and a timer circuit for the single ended read port and which is configured to generate two successive read pulses in one clock cycle for the multi-port memory.Type: GrantFiled: August 26, 2019Date of Patent: April 13, 2021Assignee: Marvell Asia Pte, Ltd.Inventors: George M. Braceras, Xiaoli Hu, Wei Zhao, Igor Arsovski, Yuzheng Jin, Hao Pu, Shuangdi Zhao, Qing Li
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Publication number: 20210065784Abstract: A structure includes a multi-port memory including a multiple transistor bitcell single ended read port and a write port, a read circuit which is connected to a multiple transistor bitcell circuit and is also configured to evaluate the multiple transistor bitcell single ended read port, and a timer circuit for the single ended read port and which is configured to generate two successive read pulses in one clock cycle for the multi-port memory.Type: ApplicationFiled: August 26, 2019Publication date: March 4, 2021Inventors: George M. BRACERAS, Xiaoli HU, Wei ZHAO, Igor ARSOVSKI, Yuzheng JIN, Hao PU, Shuangdi ZHAO, Qing LI
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Patent number: 10522217Abstract: Disclosed is a chip with a memory array and at least one positive voltage boost circuit, which provides positive voltage boost pulses to the sources of pull-up transistors in the memory cells of the array during write operations to store data values in those memory cells and, more specifically, provides positive voltage boost pulses substantially concurrently with wordline deactivation during the write operations to ensure that the data is stored. Application of such pulses to different columns can be performed using different positive voltage boost circuits to minimize power consumption. Also disclosed are a memory array operating method that employs a positive voltage boost circuit and a chip manufacturing method, wherein post-manufacture testing is performed to identify chips having memory arrays that would benefit from positive voltage boost pulses and positive voltage boost circuits are attached to those identified chips and operably connected to the memory arrays.Type: GrantFiled: August 8, 2018Date of Patent: December 31, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Venkatraghavan Bringivijayaraghavan, Eswararao Potladhurthi, George M. Braceras
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Patent number: 10510384Abstract: The present disclosure relates to a structure which includes at least one bit line restore device which is configured to precharge a bit line to a specified voltage during an intracycle time between a read operation and a write operation and is configured to be turned off during the read operation and the write operation.Type: GrantFiled: November 16, 2017Date of Patent: December 17, 2019Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Venkatraghavan Bringivijayaraghavan, George M. Braceras
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Publication number: 20190147924Abstract: The present disclosure relates to a structure which includes at least one bit line restore device which is configured to precharge a bit line to a specified voltage during an intracycle time between a read operation and a write operation and is configured to be turned off during the read operation and the write operation.Type: ApplicationFiled: November 16, 2017Publication date: May 16, 2019Inventors: Venkatraghavan BRINGIVIJAYARAGHAVAN, George M. BRACERAS
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Patent number: 9721628Abstract: Data paths are provided to a memory array. The data paths include switches for selectively aligning the data paths to different multiplexors for reading or writing to the memory array. Read data lines are steered to selected sense amplifiers based on the decode address, using the switches. Write data lines are steered to selected write drivers based on the decode address, using the switches.Type: GrantFiled: September 15, 2016Date of Patent: August 1, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Venkatraghavan Bringivijayaraghavan, George M. Braceras
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Publication number: 20170053694Abstract: Approaches for providing write-assist for a Static Random Access Memory (SRAM) array are provided. A circuit includes a control circuit connected to a cell in a SRAM array. The control circuit is configured to: apply a first voltage to a first pull down transistor of the cell during a write operation to the cell; and apply a second voltage, different than the first voltage, to a second pull down transistor of the cell during the write operation.Type: ApplicationFiled: August 21, 2015Publication date: February 23, 2017Inventors: George M. Braceras, Venkatraghavan Bringivijayaraghavan, Sheikh S. Chishti
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Patent number: 9570155Abstract: Approaches for stability of cells in a Static Random Access Memory (SRAM) array are provided. A circuit includes a precharging circuit configured to precharge bitlines of a Static Random Access Memory (SRAM) array to a first voltage potential for a non-read operation and to a second voltage potential for a read operation. The first voltage potential is different than the second voltage potential.Type: GrantFiled: June 9, 2015Date of Patent: February 14, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: George M. Braceras, Venkatraghavan Bringivijayaraghavan, Krishnan S. Rengarajan, Arjun Sankar, Sreenivasula R. Dhani Reddy
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Patent number: 9570156Abstract: Approaches for providing write-assist for a Static Random Access Memory (SRAM) array are provided. A circuit includes a control circuit connected to a cell in a SRAM array. The control circuit is configured to: apply a first voltage to a first pull down transistor of the cell during a write operation to the cell; and apply a second voltage, different than the first voltage, to a second pull down transistor of the cell during the write operation.Type: GrantFiled: August 21, 2015Date of Patent: February 14, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: George M. Braceras, Venkatraghavan Bringivijayaraghavan, Sheikh S. Chishti
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Patent number: 9548104Abstract: Approaches for providing write-assist boost for a Static Random Access Memory (SRAM) array are provided. A circuit includes a write driver of a Static Random Access Memory (SRAM) array. The circuit also includes a boost circuit that dynamically varies a write-assist boost voltage based on a stability assist setting applied to a wordline of the array.Type: GrantFiled: June 30, 2015Date of Patent: January 17, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: George M. Braceras, Venkatraghavan Bringivijayaraghavan, Krishnan S. Rengarajan, Rahul Nayak
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Publication number: 20170004874Abstract: Approaches for providing write-assist boost for a Static Random Access Memory (SRAM) array are provided. A circuit includes a write driver of a Static Random Access Memory (SRAM) array. The circuit also includes a boost circuit that dynamically varies a write-assist boost voltage based on a stability assist setting applied to a wordline of the array.Type: ApplicationFiled: June 30, 2015Publication date: January 5, 2017Inventors: George M. Braceras, Venkatraghavan Bringivijayaraghavan, Krishnan S. Rengarajan, Rahul Nayak
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Publication number: 20160365139Abstract: Approaches for stability of cells in a Static Random Access Memory (SRAM) array are provided. A circuit includes a precharging circuit configured to precharge bitlines of a Static Random Access Memory (SRAM) array to a first voltage potential for a non-read operation and to a second voltage potential for a read operation. The first voltage potential is different than the second voltage potential.Type: ApplicationFiled: June 9, 2015Publication date: December 15, 2016Inventors: George M. Braceras, Venkatraghavan Bringivijayaraghavan, Krishnan S. Rengarajan, Arjun Sankar, Sreenivasula R. Dhani Reddy
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Patent number: 9460811Abstract: A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.Type: GrantFiled: August 7, 2014Date of Patent: October 4, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: George M. Braceras, Albert M. Chu, Kevin W. Gorman, Michael R. Ouellette, Ronald A. Piro, Daryl M. Seitzer, Rohit Shetty, Thomas W. Wyckoff
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Patent number: 9437282Abstract: A sense amplifier device for sensing a differential signal produced by a memory cell includes a first n-type metal-oxide-semiconductor field-effect transistor (NMOS) stack having multiple NMOS devices sharing a gate connection connected to a complementary data line; and a second NMOS stack having multiple NMOS devices sharing a gate connection connected to a true data line. At least one of the devices in the first stack has higher gate-to-source and drain-to-source voltages than a gate-to-source and drain-to-source voltages of at least one device in the second stack when the voltage of the complementary data line is higher than the true data line. At least one of the devices in the second stack has a higher gate-to-source and drain-to-source voltages than the gate-to-source and drain-to-source voltages of at least one device in the first stack when the voltage of the true data line is higher than the complementary data line.Type: GrantFiled: August 6, 2015Date of Patent: September 6, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: George M. Braceras, Venkatraghavan Bringivijayaraghavan, Krishnan S. Rengarajan
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Patent number: 9390769Abstract: Multiplexed latches include a multiplexor having a first data input, a second data input, a selection input, and a multiplexor output. A first latch has a first latch clock input, and a first latch output. A second latch has a second latch clock input, and a second latch output. The first latch output is connected to the first data input of the multiplexor, and the second latch output is connected to the second data input of the multiplexor. A feedback loop connects the multiplexor output to the first latch clock input and the second latch clock input. When the selection signal is received by the multiplexor, the feedback loop feeds the output from the multiplexor back to the latches to maintain the existing latch output until the clock signal transitions, to avoid glitches in the multiplexor output when the selection signal and clock signal are not synchronized.Type: GrantFiled: October 26, 2015Date of Patent: July 12, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Vinay Bhatsoori, George M. Braceras, Venkatraghavan Bringivijayaraghavan
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Patent number: 9236116Abstract: Memory cells with read assist schemes and methods of use are provided. The memory includes a plurality of rows and columns, each of which include a memory cell having a pull-down device. The memory further includes at least one boost circuit connected to each of the memory cells and which provides a negative boost signal to the pull-down devices during read access.Type: GrantFiled: March 26, 2015Date of Patent: January 12, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: George M. Braceras, Venkatraghavan Bringivijayaraghavan, Binu Jose, Krishnan S. Rengarajan
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Publication number: 20140351662Abstract: A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.Type: ApplicationFiled: August 7, 2014Publication date: November 27, 2014Inventors: George M. BRACERAS, Albert M. CHU, Kevin W. GORMAN, Michael R. OUELLETTE, Ronald A. PIRO, Daryl M. SEITZER, Rohit SHETTY, Thomas W. WYCKOFF
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Patent number: 8839054Abstract: A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.Type: GrantFiled: April 12, 2012Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: George M. Braceras, Albert M. Chu, Kevin W. Gorman, Michael R. Ouellette, Ronald A. Piro, Daryl M. Seitzer, Rohit Shetty, Thomas W. Wyckoff
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Patent number: 8654594Abstract: An integrated circuit structure comprises a static random access memory (SRAM) structure and a logic circuit. A power supply is operatively connected to the SRAM structure, and provides a first voltage to the SRAM structure. A voltage limiter is operatively connected to the power supply. The voltage limiter comprises a switching device operatively connected to the power supply. The switching device receives the first voltage and a second voltage supplied to structures external to the SRAM structure. A resistive element is operatively connected to the switching device. The switching device connects the resistive element to the power supply. The resistive element is selected to enable an output from the switching device to the logic circuit when a difference between the first voltage and the second voltage is greater than a voltage threshold value of the switching device.Type: GrantFiled: February 23, 2012Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: Igor Arsovski, George M. Braceras, Harold Pilo
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Patent number: 8630139Abstract: Disclosed is a memory array in which the lower of two supply voltages from two power supplies is dynamically selected for bitline pre-charge operations. In the memory array, a voltage comparator compares the first supply voltage on a first power supply rail to a second supply voltage on a second power supply rail and outputs a voltage difference signal. If the voltage difference signal has a first value indicating that the first supply voltage is equal to or less than the second supply voltage, than a control circuit ensures that the complementary bitlines connected to a memory cell are pre-charged to the first supply voltage. If the voltage difference signal has a second value indicating that the first supply voltage is greater than the second supply voltage, then the control circuit ensures that the complementary bitlines are pre-charged to the second supply voltage. Also disclosed is an associated method.Type: GrantFiled: November 30, 2011Date of Patent: January 14, 2014Assignee: International Business Machines CorporationInventors: George M. Braceras, Kirk D. Peterson, Harold Pilo