Abstract: A process for selectively hardening a surface layer of a polymeric photoresist to make such surface layer opaque and insoluble in photoresist carrier solvents, where such selectivity is coextensive with the polymeric/monomeric pattern created in the photoresist. Representative hardening processes include controlled exposure to certain gas plasmas, ion bombardment, or irradiation by ultraviolet radiation of chosen wavelength range. The selectively hardened polymeric regions act as a barrier to the carrier solvent in which the polymer film is laid down and to the developer subsequently employed to remove the monomeric regions. The hardened polymeric regions further exhibit an actinic radiation barrier property preventing radiation depolymerization. In one form the process may be used in a two-layer photoresist structure, where the pinhole-covering thicker second layer is laid down and exposed before developing the monomeric regions of the thinner first layer.

Abstract: A simplified small geometry MOS process incorporates a tungsten shunt layer on the thin silicon gate electrode layer allowing reduction of the thickness of the silicon layer and the use of an implant through the layer to form precisely controlled shallow source/drain regions without channeling. Lightly doped extension of the source and drain regions are automatically formed by an LDD implant following an isotropic undercutting etch of the silicon. The process is readily adapted to optional guard band implants and other beneficial structures such as gate sidewall oxide spacers.

Abstract: A process for fabricating aligned, stacked CMOS devices. Following the formation of the lower FET device, conformal undoped and doped oxide layers are formed thereover so that the level of the upper surface of the common gate electrode is above the doped oxide as formed in the source and drain regions of the lower FET device. A planarizing photoresist is then deposited and etched in conjunction with the oxide to the upper surface of the gate electrode. The exposed gate electrode is covered with a gate oxide layer, and a polycrystalline silicon layer for recrystallization to an upper FET device. Updiffusion from the residuals of doped oxide then creates an upper FET device with source and drain regions aligned to the gate oxide thereof and the underlying common gate electrode.

Abstract: Various structural patterns of alignment keys particularly suited for aligning masks and wafers during the fabrication of semiconductor devices. Each alignment key includes an orthogonal arrangement of bar-shaped segments. The relative dimensions of the mask and wafer alignment keys ensure a partial overlap and coaxial positioning of the bar-shaped segments when the keys are fully aligned. Precise optical alignment of the mask and wafer keys is evidenced by visually perceived edge diffraction effects. The invention also encompasses a systematic method for aligning representative structural patterns.

Abstract: A process for beveling the sharp corners on an integrated circuit metal layer, which corners were created by commonly practiced masking and etching steps. In one form, the photoresist mask used to etch the lower level metal pattern is retained on the wafer as during the beveling operation. With a positive photoresist and an aluminum alloy metal lower level layer, an etch with an alkaline photoresist solvent will isotropically remove both photoresist and metal, but at a controlled difference in rate. Beveling of the metal corners suppresses the reentry effect otherwise encountered when subsequent dielectric materials are deposited over the lower level metal layer.