Patents by Inventor George Matamis

George Matamis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220189570
    Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.
    Type: Application
    Filed: December 10, 2020
    Publication date: June 16, 2022
    Inventors: Kalyan Chakravarthy Kavalipurapu, George Matamis, Yingda Dong, Chang H. Siau
  • Publication number: 20220157844
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a construction comprising a stack that have vertically-alternating insulative tiers and wordline tiers. An array of openings is formed in an uppermost portion of upper material that is above the stack, and the openings comprise channel openings and dummy openings. At least the uppermost portion of the upper material is used as a mask while etching the channel openings and the dummy openings into a lower portion of the upper material. The channel openings are etched into the insulative and wordline tiers. The channel openings are etched deeper into the construction than the dummy openings, and channel material is formed in the channel openings after the etching. Structures independent of method are disclosed.
    Type: Application
    Filed: February 1, 2022
    Publication date: May 19, 2022
    Applicant: Micron Technology, Inc.
    Inventors: M. Jared Barclay, Merri L. Carlson, Saurabh Keshav, George Matamis, Young Joon Moon, Kunal R. Parekh, Paolo Tessariol, Vinayak Shamanna
  • Publication number: 20220149068
    Abstract: An electronic device comprises a stack of alternating dielectric materials and conductive materials, a pillar region extending vertically through the stack, an oxide material within the pillar region and laterally adjacent to the dielectric materials and the conductive materials of the stack, and a storage node laterally adjacent to the oxide material and within the pillar region. A charge confinement region of the storage node is in horizontal alignment with the conductive materials of the stack. A height of the charge confinement region in a vertical direction is less than a height of a respective, laterally adjacent conductive material of the stack in the vertical direction. Related methods and systems are also disclosed.
    Type: Application
    Filed: November 9, 2020
    Publication date: May 12, 2022
    Inventors: Yifen Liu, Yan Song, Albert Fayrushin, Naiming Liu, Yingda Dong, George Matamis
  • Publication number: 20220139958
    Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.
    Type: Application
    Filed: January 20, 2022
    Publication date: May 5, 2022
    Inventors: Yifen Liu, Tecla Ghilardi, George Matamis, Justin D. Shepherdson, Nancy M. Lomeli, Chet E. Carter, Erik R. Byers
  • Patent number: 11302634
    Abstract: Microelectronic devices include stadium structures within a stack structure and substantially symmetrically distributed between a first pillar structure and a second pillar structure, each of which vertically extends through the stack structure. The stack structure includes a vertically alternating sequence of insulative materials and conductive materials arranged in tiers. Each of the stadium structures includes staircase structures having steps including lateral ends of some of the tiers. The substantially symmetrical distribution of the stadium structures, and fill material adjacent such structures, may substantially balance material stresses to avoid or minimize bending of the adjacent pillars. Related methods and systems are also disclosed.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Lifang Xu, Jian Li, Graham R. Wolstenholme, Paolo Tessariol, George Matamis, Nancy M. Lomeli
  • Patent number: 11271002
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a construction comprising a stack that have vertically-alternating insulative tiers and wordline tiers. An array of openings is formed in an uppermost portion of upper material that is above the stack, and the openings comprise channel openings and dummy openings. At least the uppermost portion of the upper material is used as a mask while etching the channel openings and the dummy openings into a lower portion of the upper material. The channel openings are etched into the insulative and wordline tiers. The channel openings are etched deeper into the construction than the dummy openings, and channel material is formed in the channel openings after the etching. Structures independent of method are disclosed.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: March 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: M. Jared Barclay, Merri L. Carlson, Saurabh Keshav, George Matamis, Young Joon Moon, Kunal R. Parekh, Paolo Tessariol, Vinayak Shamanna
  • Patent number: 11264404
    Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: March 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Yifen Liu, Tecla Ghilardi, George Matamis, Justin D. Shepherdson, Nancy M. Lomeli, Chet E. Carter, Erik R. Byers
  • Publication number: 20220045086
    Abstract: Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: August 4, 2020
    Publication date: February 10, 2022
    Applicant: Micron Technology, Inc.
    Inventors: S.M. Istiaque Hossain, Prakash Rau Mokhna Rau, Arun Kumar Dhayalan, Damir Fazil, Joel D. Peterson, Anilkumar Chandolu, Albert Fayrushin, George Matamis, Christopher Larsen, Rokibul Islam
  • Publication number: 20210399006
    Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.
    Type: Application
    Filed: June 17, 2020
    Publication date: December 23, 2021
    Inventors: Yifen Liu, Tecla Ghilardi, George Matamis, Justin D. Shepherdson, Nancy M. Lomeli, Chet E. Carter, Erik R. Byers
  • Publication number: 20210257298
    Abstract: Microelectronic devices include stadium structures within a stack structure and substantially symmetrically distributed between a first pillar structure and a second pillar structure, each of which vertically extends through the stack structure. The stack structure includes a vertically alternating sequence of insulative materials and conductive materials arranged in tiers. Each of the stadium structures includes staircase structures having steps including lateral ends of some of the tiers. The substantially symmetrical distribution of the stadium structures, and fill material adjacent such structures, may substantially balance material stresses to avoid or minimize bending of the adjacent pillars. Related methods and systems are also disclosed.
    Type: Application
    Filed: February 13, 2020
    Publication date: August 19, 2021
    Inventors: Lifang Xu, Jian Li, Graham R. Wolstenholme, Paolo Tessariol, George Matamis, Nancy M. Lomeli
  • Publication number: 20210242032
    Abstract: Various embodiments herein relate to methods, apparatus, and systems for etching a feature in a substrate. Typically the feature is etched in a dielectric-containing stack. The etching process involves cyclically etching the feature and depositing a protective film on sidewalls of the partially etched feature. These stages are repeated until the feature reaches its final depth. The protective film may have a particular composition, for example including at least one of a tungsten carbonitride, a tungsten sulfide, tin, a tin-containing compound, molybdenum, a molybdenum-containing compound, a ruthenium carbonitride, a ruthenium sulfide, an aluminum carbonitride, an aluminum sulfide, zirconium, and a zirconium-containing compound. A number of optional steps may be taken including, for example, doping the mask layer, pre-treating the substrate prior to deposition, removing the protective film from the sidewalls, and oxidizing any remaining protective film.
    Type: Application
    Filed: August 19, 2019
    Publication date: August 5, 2021
    Inventors: Karthik S. COLINJIVADI, Samantha SiamHwa TAN, Shih-Ked LEE, George MATAMIS, Yongsik YU, Yang PAN, Patrick VAN CLEEMPUT, Akhil SINGHAL, Juwen GAO, Raashina HUMAYUN
  • Publication number: 20210082806
    Abstract: Some embodiments include an assembly having a memory stack which includes dielectric levels and conductive levels. A select gate structure is over the memory stack. A trench extends through the select gate structure. The trench has a first side and an opposing second side, along a cross-section. The trench splits the select gate structure into a first select gate configuration and a second select gate configuration. A void is within the trench and is laterally between the first and second select gate configurations. Channel material pillars extend through the memory stack. Memory cells are along the channel material pillars.
    Type: Application
    Filed: September 18, 2019
    Publication date: March 18, 2021
    Applicant: Micron Technology, Inc.
    Inventors: John D. Hopkins, George Matamis
  • Publication number: 20200328222
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a construction comprising a stack that have vertically-alternating insulative tiers and wordline tiers. An array of openings is formed in an uppermost portion of upper material that is above the stack, and the openings comprise channel openings and dummy openings. At least the uppermost portion of the upper material is used as a mask while etching the channel openings and the dummy openings into a lower portion of the upper material. The channel openings are etched into the insulative and wordline tiers. The channel openings are etched deeper into the construction than the dummy openings, and channel material is formed in the channel openings after the etching. Structures independent of method are disclosed.
    Type: Application
    Filed: April 12, 2019
    Publication date: October 15, 2020
    Applicant: Micron Technology, Inc.
    Inventors: M. Jared Barclay, Merri L. Carlson, Saurabh Keshav, George Matamis, Young Joon Moon, Kunal R. Parekh, Paolo Tessariol, Vinayak Shamanna
  • Patent number: 10170324
    Abstract: Methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate are provided. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective film on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective film may be deposited under different conditions (e.g., pressure, duration of reactant delivery, duration of plasma exposure, RF power, and/or RF duty cycle, etc.) in different deposition operations. Such conditions may affect the degree of conformality at which the protective film forms. In various embodiments, one or more protective films may be sub-conformal. In these or other embodiments, one or more other protective films may be conformal.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: January 1, 2019
    Assignee: Lam Research Corporation
    Inventors: Nikhil Dole, Eric A. Hudson, George Matamis
  • Patent number: 10128261
    Abstract: A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: November 13, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Rahul Sharangpani, Sateesh Koka, Genta Mizuno, Naoki Takeguchi, Senaka Krishna Kanakamedala, George Matamis, Yao-Sheng Lee, Johann Alsmeier
  • Patent number: 9837286
    Abstract: A method for selectively etching a tungsten layer on a substrate includes arranging a substrate including a tungsten layer on a substrate support. The substrate processing chamber includes an upper chamber region, an inductive coil arranged outside of the upper chamber region, a lower chamber region including the substrate support and a gas dispersion device arranged between the upper and lower chamber regions. The gas dispersion device includes a plurality of holes in fluid communication with the upper and lower chamber regions. The method further includes controlling pressure in the substrate processing chamber in a range from 0.4 Torr to 10 Torr; supplying an etch gas mixture including fluorine-based gas to the upper chamber region; striking inductively coupled plasma in the upper chamber region by supplying power to the inductive coil; and selectively etching the tungsten layer relative to at least one other film material of the substrate.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: December 5, 2017
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Dengliang Yang, Helen H. Zhu, George Matamis, Brad Jacobs, Joon Hong Park, Joydeep Guha
  • Patent number: 9806090
    Abstract: A method of making a monolithic three dimensional NAND string which contains a semiconductor channel and a plurality of control gate electrodes, includes selectively forming a plurality of discrete charge storage regions using atomic layer deposition. The plurality of discrete charge storage regions includes at least one of a metal or an electrically conductive metal oxide.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: October 31, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, Thomas Jongwan Kwon, Senaka Kanakamedala, George Matamis
  • Publication number: 20170287925
    Abstract: A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A cobalt portion can be formed in each backside recess. Each backside recess can be filled with a cobalt portion alone, or can be filled with a combination of a cobalt portion and a metallic material portion including a material other than cobalt.
    Type: Application
    Filed: February 4, 2015
    Publication date: October 5, 2017
    Inventors: Raghuveer S. MAKALA, Rahul SHARANGPANI, Sateesh KOKA, Genta MIZUNO, Naoki TAKEGUCHI, Senaka Krishna KANAKAMEDALA, George MATAMIS, Yao-Sheng LEE, Johann ALSMEIER
  • Patent number: 9780182
    Abstract: A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A molybdenum-containing portion can be formed in each backside recess. Each backside recess can be filled with a molybdenum-containing portion alone, or can be filled with a combination of a molybdenum-containing portion and a metallic material portion including a material other than molybdenum.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: October 3, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Somesh Peri, Raghuveer S. Makala, Sateesh Koka, Yao-Sheng Lee, Johann Alsmeier, George Matamis
  • Patent number: 9698223
    Abstract: A memory film and a semiconductor channel are formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, electrically conductive layers are formed in the backside recesses. Each electrically conductive layer includes a combination of a tensile-stress-generating metallic material and a compressive-stress-generating metallic material. The tensile-stress-generating metallic material may be ruthenium and the compressive-stress-generating metallic material may be tungsten. An anneal may be performed to provide an alloy of the compressive-stress-generating metallic material and the tensile-stress-generating metallic material.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: July 4, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rahul Sharangpani, Raghuveer S. Makala, George Matamis