Abstract: An auxiliary circuit for providing current to an external device includes a first switch disposed between a first node and a second node. The first switch is configured to electrically couple the first node to the second node when a first voltage exceeds a first threshold. A comparison circuit has an input coupled to the second node and is configured to compare a second voltage at the input to a second threshold. A second switch has a control terminal coupled to an output of the comparison circuit, a first terminal coupled to a source, and a second terminal for coupling to the external device. The comparison circuit is configured to provide a third voltage at control terminal when the second voltage exceeds the second threshold. The second switch is configured to provide the current from the source to the external device when the third voltage exceeds a threshold of the second switch.

Abstract: A rate based FIFO controller identifies a time slot value for a number of time slots allocated for receiving or transmitting data in a frame and selects data fill level threshold values in a FIFO according to the time slot value. Data is then written into and read out of the FIFO according to a comparison of the data fill level in the FIFO with the threshold values.

Abstract: A test circuit receives a reference signal having a reference frequency and generates a synchronizer input signal having a synchronizer input frequency for inputting into a synchronizer circuit. A frequency generator is configured to offset the synchronizer input frequency at selectable frequencies from a nominal frequency value. An offset measurement circuit is configured to compare the frequency offset for the synchronizer input frequency with the frequency offset of a synchronizer output signal.

Abstract: A method and apparatus are described for interfacing between a physical layer (PHY) interface and a bus. For the receiver side, a downstream clock signal from a physical layer transceiver and a cell available signal in a first plurality of receiver signals from the PHY interface are received. Bus receiver signals to the bus and a second plurality of receiver signals to the PHY interface are generated using the downstream clock signal and the cell available signal. For the transmitter side, an upstream clock signal from a physical layer transceiver, first plurality of bus transmitter signals from the bus, and a cell available signal in a first plurality of PHY transmitter signals from the PHY interface are received. A second plurality of bus transmitter signals to the bus and a second plurality of PHY transmitter signals to the physical interface are generated using the upstream clock signal and the cell available signal.