Patents by Inventor George Nakane

George Nakane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7850086
    Abstract: The present invention extends the reading range between a contactless type information medium (semiconductor integrated circuit) and a reader/writer, which exchanges data in contactless communications with the contactless type information medium, and enables a stable data exchange even if the power supply voltage is lowered when data is returned from the contactless type information medium to the reader/writer. Specifically, when data is returned from the contactless type information medium, the data to be returned is held in the logic circuit section 200 capable of operating at a lower voltage than the non-volatile memory circuit section 300, and the reset detection lower limit voltage to be used by the reset generating circuit 160 during the data-returning period is set to be lower than that during periods other than the data-returning period.
    Type: Grant
    Filed: April 12, 2005
    Date of Patent: December 14, 2010
    Assignee: Panasonic Corporation
    Inventors: George Nakane, Tatsumi Sumi
  • Patent number: 7711917
    Abstract: A semiconductor device according to the present invention comprises a first non-volatile memory, a second non-volatile memory in which initial data is stored, and an initialization controller for initializing the first non-volatile memory, wherein the second non-volatile memory has anti-stress properties higher than those of the first non-volatile memory, and the initialization controller reads the initial data from the second non-volatile memory when the first non-volatile memory is initialized and copies the read initial data in the first non-volatile memory to thereby initialize the first non-volatile memory.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: May 4, 2010
    Assignee: Panasonic Corporation
    Inventors: Kazuki Yoshioka, George Nakane, Yoshitaka Mano
  • Publication number: 20080059703
    Abstract: A semiconductor device according to the present invention comprises a first non-volatile memory, a second non-volatile memory in which initial data is stored, and an initialization controller for initializing the first non-volatile memory, wherein the second non-volatile memory has anti-stress properties higher than those of the first non-volatile memory, and the initialization controller reads the initial data from the second non-volatile memory when the first non-volatile memory is initialized and copies the read initial data in the first non-volatile memory to thereby initialize the first non-volatile memory.
    Type: Application
    Filed: September 5, 2007
    Publication date: March 6, 2008
    Inventors: Kazuki Yoshioka, George Nakane, Yoshitaka Mano
  • Publication number: 20070188297
    Abstract: The present invention extends the reading range between a contactless type information medium (semiconductor integrated circuit) and a reader/writer, which exchanges data in contactless communications with the contactless type information medium, and enables a stable data exchange even if the power supply voltage is lowered when data is returned from the contactless type information medium to the reader/writer. Specifically, when data is returned from the contactless type information medium, the data to be returned is held in the logic circuit section 200 capable of operating at a lower voltage than the non-volatile memory circuit section 300, and the reset detection lower limit voltage to be used by the reset generating circuit 160 during the data-returning period is set to be lower than that during periods other than the data-returning period.
    Type: Application
    Filed: April 12, 2005
    Publication date: August 16, 2007
    Inventors: George Nakane, Tatsumi Sumi
  • Patent number: 7138699
    Abstract: A semiconductor integrated circuit includes a supply voltage generator for rectifying a signal received by an antenna coil and generating a supply voltage set at a predetermined voltage by a regulator, and a demodulator. The demodulator includes a demodulation circuit for demodulating an input signal and outputting the demodulated input signal, a resistor whose one end is connected to one end of the antenna coil, a diode whose anode is connected to the other end of the resistor and whose cathode is connected to a node located to the input end of the demodulation circuit, a first capacitance connected between a node at which the resistor and the diode are connected to each other and a grounding conductor, and a second capacitance connected between a node at which the diode and the demodulation circuit are connected to each other and a grounding conductor.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: November 21, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: George Nakane, Tatsumi Sumi
  • Patent number: 7023261
    Abstract: A semiconductor memory device includes a voltage reduction circuit which reduces a power supply voltage and outputs an internal voltage, a nonvolatile memory connected to the internal voltage and a current consumption control circuit including a switch transistor and a resistor. In this case, the amount of electric current which the nonvolatile memory consumes and the amount of electric current which the resistor consumes are substantially the same. When the nonvolatile memory is in a non-operation state, the current consumption control circuit turns ON the switch transistor by a memory activation signal and consumes substantially the same amount of electric current as the amount of electric current which the nonvolatile memory consumes. When the nonvolatile memory is in an operation state, the current consumption control circuit turns OFF the switch transistor and stops electric current consumption by the resistor.
    Type: Grant
    Filed: January 5, 2004
    Date of Patent: April 4, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshitaka Mano, George Nakane
  • Publication number: 20060022041
    Abstract: A semiconductor integrated circuit includes a supply voltage generator for rectifying a signal received by an antenna coil and generating a supply voltage set at a predetermined voltage by a regulator, and a demodulator. The demodulator includes a demodulation circuit for demodulating an input signal and outputting the demodulated input signal, a resistor whose one end is connected to one end of the antenna coil, a diode whose anode is connected to the other end of the resistor and whose cathode is connected to a node located to the input end of the demodulation circuit, a first capacitance connected between a node at which the resistor and the diode are connected to each other and a grounding conductor, and a second capacitance connected between a node at which the diode and the demodulation circuit are connected to each other and a grounding conductor.
    Type: Application
    Filed: September 8, 2003
    Publication date: February 2, 2006
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: George Nakane, Tatsumi Sumi
  • Patent number: 6848620
    Abstract: A semiconductor integrated circuit is provided to allow a stable operation even in a short distance where an IC card is in contact with a reader/writer. In a semiconductor integrated circuit for a noncontact IC card that obtains driving power supply by carrying superimposed data, obtained voltage does not become overvoltage and data can be demodulated with stability regardless of a change in communication distance. Inputs of a system (including a rectifier circuit and a power supply circuit) producing power supply from an antenna coil of the IC card which receives radio waves transmitted from a reader/writer, and of a demodulator circuit are connected via a path separated from the output of the rectifier circuit. Thus, a power supply voltage range can be set within a permissible value and a rate of change in input of the demodulator circuit can be obtained regardless whether the communication distance is short or long.
    Type: Grant
    Filed: April 10, 2002
    Date of Patent: February 1, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: George Nakane, Tatsumi Sumi
  • Patent number: 6838891
    Abstract: A semiconductor device includes a plurality of semiconductor integrated circuits formed on a semiconductor wafer; an testing pad for inputting and outputting a signal to and from an internal circuit of the semiconductor integrated circuit; a switch for switching a state of a connection between the semiconductor integrated circuit and the testing pad; and a wiring pattern formed on a parting line around the semiconductor integrated circuit and connected to an input terminal of the switch. When the semiconductor integrated circuits are separated, cutting off of the wiring pattern causes the switch to be turned off, so that the internal circuit is prevented from being affected by the influence of the cutting plane.
    Type: Grant
    Filed: April 9, 2002
    Date of Patent: January 4, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsuyoshi Ohya, George Nakane
  • Publication number: 20040135624
    Abstract: A semiconductor memory device includes a voltage reduction circuit which reduces a power supply voltage and outputs an internal voltage, a nonvolatile memory connected to the internal voltage and a current consumption control circuit including a switch transistor and a resistor. In this case, the amount of electric current which the nonvolatile memory consumes and the amount of electric current which the resistor consumes are substantially the same. When the nonvolatile memory is in a non-operation state, the current consumption control circuit turns ON the switch transistor by a memory activation signal and consumes substantially the same amount of electric current as the amount of electric current which the nonvolatile memory consumes. When the nonvolatile memory is in an operation state, the current consumption control circuit turns OFF the switch transistor and stops electric current consumption by the resistor.
    Type: Application
    Filed: January 5, 2004
    Publication date: July 15, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yoshitaka Mano, George Nakane
  • Publication number: 20030145216
    Abstract: The present invention provides a smaller non-contact IC card that includes a counter for measuring time from when the non-contact IC card enters communication coverage of a reader/writer until it actually receives a command from the reader/writer. By using the time measured by the counter as a random-number value, a high-speed, aperiodic, equally random and hard-to-predict random-number data can be generated, thus achieving minimization of non-contact IC cards.
    Type: Application
    Filed: December 20, 2002
    Publication date: July 31, 2003
    Applicant: Matsushita Elec. Ind. Co., Ltd.
    Inventors: George Nakane, Mitsuyoshi Ohya
  • Publication number: 20020153997
    Abstract: A semiconductor integrated circuit is provided to allow a stable operation even in a short distance where an IC card is in contact with a reader/writer. In a semiconductor integrated circuit for a noncontact IC card that obtains driving power supply by carrying superimposed data, obtained voltage does not become overvoltage and data can be demodulated with stability regardless of a change in communication distance. Inputs of a system (including a rectifier circuit and a power supply circuit) producing power supply from an antenna coil of the IC card which receives radio waves transmitted from a reader/writer, and of a demodulator circuit are connected via a path separated from the output of the rectifier circuit. Thus, a power supply voltage range can be set within a permissible value and a rate of change in input of the demodulator circuit can be obtained regardless whether the communication distance is short or long.
    Type: Application
    Filed: April 10, 2002
    Publication date: October 24, 2002
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: George Nakane, Tatsumi Sumi
  • Publication number: 20020145440
    Abstract: A semiconductor device includes a plurality of semiconductor integrated circuits formed on a semiconductor wafer; an testing pad for inputting and outputting a signal to and from an internal circuit of the semiconductor integrated circuit; a switch for switching a state of a connection between the semiconductor integrated circuit and the testing pad; and a wiring pattern formed on a parting line around the semiconductor integrated circuit and connected to an input terminal of the switch. When the semiconductor integrated circuits are separated, cutting off of the wiring pattern causes the switch to be turned off, so that the internal circuit is prevented from being affected by the influence of the cutting plane.
    Type: Application
    Filed: April 9, 2002
    Publication date: October 10, 2002
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsuyoshi Ohya, George Nakane
  • Patent number: 6067265
    Abstract: A reference potential generator is constituted of two signal lines 21 and 22; a charge supplier to supply charge to signal lines 21 and 22; connectors 24a and 24b connecting the charge supplier 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a connector 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, "1" or "0" of readout data can be precisely determined.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: May 23, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshio Mukunoki, Hiroshige Hirano, George Nakane, Tetsuji Nakakuma, Tatsumi Sumi, Nobuyuki Moriwaki
  • Patent number: 5953277
    Abstract: A reference potential generator is constituted of two signal lines 21 and 22; a charge supplying circuit to supply charge to signal lines 21 and 22; a first connection circiut 24a and 24b connecting the charge supplying circuit 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a second connection circuit 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, "1" or "0" of readout data can be precisely determined.
    Type: Grant
    Filed: March 10, 1998
    Date of Patent: September 14, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshio Mukunoki, Hiroshige Hirano, George Nakane, Tetsuji Nakakuma, Tatsumi Sumi, Nobuyuki Moriwaki
  • Patent number: 5828615
    Abstract: A reference potential generator is constituted of two signal lines 21 and 22; a charge supplying means to supply charge to signal lines 21 and 22; a first connection circuit 24a and 24b connecting the charge supplying circuit 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a second connection circuit 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, "1" or "0" of readout data can be precisely determined.
    Type: Grant
    Filed: January 8, 1997
    Date of Patent: October 27, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshio Mukunoki, Hiroshige Hirano, George Nakane, Tetsuji Nakakuma, Tatsumi Sumi, Nobuyuki Moriwaki
  • Patent number: 5751628
    Abstract: A memory cell comprises a ferroelectric capacitor, first main memory cells are connected to a first bit line, a first reference memory cell is connected to a second bit line, second main memory cells are connected to the second bit line, and a second reference memory cell is connected to the first bit line. When a first operation mode is selected by a control circuit comprising NAND gates and NOR gates, first main memory cells and first reference memory cell are selected, and when a second operation mode is selected, first main memory cells and second main memory cells are selected. Thus, by switching the operation between the two operation modes, a ferroelectric memory device that has stable operation at a low voltage and high integration at a high voltage is provided.
    Type: Grant
    Filed: August 20, 1996
    Date of Patent: May 12, 1998
    Assignee: Matsushita Electronics Corporation
    Inventors: Hiroshige Hirano, Nobuyuki Moriwaki, Tetsuji Nakakuma, Toshiyuki Honda, George Nakane
  • Patent number: 5546342
    Abstract: The life of a semiconductor memory device can be prolonged by using a plurality of memory cells and decreasing the stress applied to the dielectric film of the memory cells storing a data value "1." This is achieved in the present invention by decreasing the number of rewritings required to retain stored data. Specifically, the present invention utilizes a reverse and rewrite means to reverse and rewrite data back into memory cells after being read, memory means for memorizing a signal indicating whether the currently stored data is in a reversed state, and judging means for judging whether the data should be reversely output.
    Type: Grant
    Filed: October 13, 1994
    Date of Patent: August 13, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: George Nakane, Toshio Mukunoki, Nobuyuki Moriwaki, Tatsumi Sumi, Hiroshige Hirano, Tetsuji Nakakuma
  • Patent number: 5523974
    Abstract: A semiconductor memory device comprises a main memory cell, a redundant memory cell, a redundant address data cell comprising a non-volatile memory which electrically memorizes an address of a redundant memory cell which replaced a failed memory cell in the main memory cell, a control circuit 15 and a redundant memory cell selecting circuit 16. The redundant memory cell selecting circuit serves to hold first address data which has been read from the redundant address data cell, and to compare the first address data with second address data for a read or write operation which is input via the control circuit and thereby select the main memory cell or the redundant memory cell.
    Type: Grant
    Filed: November 21, 1994
    Date of Patent: June 4, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroshige Hirano, George Nakane, Tetsuji Nakakuma, Nobuyuki Moriwaki, Toshio Mukunoki, Tatsumi Sumi
  • Patent number: 5515312
    Abstract: A semiconductor memory device comprising a pair of bit lines, a word line, a cell plate electrode, a memory cell connected to each of the bit lines, the word line and the cell plate electrode, and a prevention means that permits only a predetermined number of readouts of data stored in the memory cell, after which the data is destroyed and is not retrieved with subsequent readout attempts.
    Type: Grant
    Filed: October 13, 1994
    Date of Patent: May 7, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tetsuji Nakakuma, Tatsumi Sumi, Hiroshige Hirano, George Nakane, Nobuyuki Moriwaki, Toshio Mukunoki