Abstract: A method and apparatus are provided for error correction of a memory by using a first memory (18) and second memory (14) to perform error correction code (ECC) processing on data retrieved from the first memory and to use status control bits (35-37) in the second memory to detect and manage hard and soft errors identified by the ECC processing.

Abstract: A memory device includes a plurality of sense amplifiers, an array of memory cells including a first subset of memory cells, and a plurality of word lines. Each word line is coupled to each memory cell in a respective row of the memory cells and each row of the memory cells includes one memory cell of the first subset of memory cells. Each of a plurality of control word lines is coupled to a respective one of the memory cells in the first subset of memory cells and each of the memory cells in the first subset of memory cells generates a sense amplifier control signal coupled to control operation of a respective one of the plurality of sense amplifiers.

Abstract: A memory system includes a memory and a content addressable memory (CAM). The memory includes a plurality of address locations, wherein each address location configured to store data and one or more error correction bits corresponding to the data. The CAM includes a plurality of entries, wherein each entry configured to store an address value of an address location of the memory and one or more extended error correction bits corresponding to the data stored at the address location of the memory.

Abstract: A memory having a memory array having a plurality of word lines, a plurality of bit cells coupled to the word lines, and a plurality of control memory cells coupled to the word lines. Each word line of the plurality of word lines has a control memory cell coupled thereto and each control memory cell has an output. The memory also has a plurality of logic circuits coupled to the plurality of word lines. The output of each control memory cell is coupled to a corresponding one of the plurality of logic circuits. The plurality of logic circuits prevents access to the word line selected by a row address if the output of the control memory cell coupled to the selected word line is in a first logic state.

Abstract: In accordance with at least one embodiment, column level power control granularity is provided to control a low power state of a memory using a drowsy column control bit to control the low power state at an individual column level to protect the memory from weak bit failure. In accordance with at least one embodiment, a method of using a dedicated row of bit cells in a memory array is provided wherein each bit in the row controls the low power state of a respective column in the array. A special control signal is used to access the word line, and the word line is outside of the regular word line address space. A mechanism is provided to designate the weak bit column and set the control bit corresponding to that particular column to disable the drowsy/low power state for that column.

Abstract: A dynamic logic circuit includes an N channel transistor stack between a dynamic node and a first power supply terminal for receiving a plurality of logic signals. A P channel clock transistor is coupled between a second power supply terminal and the dynamic node is for receiving a clock signal. An N channel clock transistor is in series with the N channel stack and is between the dynamic node and the first power supply terminal is for receiving the clock signal. A keeper transistor has a first current electrode coupled to the dynamic node, a second current electrode coupled to a second power supply terminal, and a control electrode. A static logic circuit has an output for providing an output responsive to a state of the logic signals. The output is coupled to the control electrode of the keeper transistor.

Abstract: A dynamic logic circuit includes an N channel transistor stack between a dynamic node and a first power terminal for receiving a plurality of logic signals. A first clock transistor is coupled between a second power terminal and the dynamic node for receiving a clock signal. A second clock transistor is in series with the N channel stack, between the dynamic node and a second power terminal, and for receiving the clock signal. An inverter circuit has an input coupled to the dynamic node and an output. A keeper transistor has a control electrode coupled to the output of the inverter circuit, a first current electrode coupled to the dynamic node, and a second current electrode. A plurality of P channel transistors, which are coupled in parallel, are coupled between the keeper transistor and the second power terminal and are for receiving the plurality of logic signals.

Abstract: A method is provided for error correction of a memory. The method includes: providing a first memory and a second memory; initiating a read operation of the first memory to retrieve data; performing an error correction code (ECC) processing on the data, wherein the ECC processing for determining that at least a portion of the data is erroneous and for providing corrected data; and determining if an address of the erroneous data is stored in the second memory, if the address of the erroneous data is stored in the second memory, storing the corrected data in the second memory, and if the address of the erroneous data is not stored in the second memory, storing the address in the second memory.

Abstract: A method for refreshing a Dynamic Random Access Memory (DRAM) includes performing a refresh on at least a portion of the DRAM at a first refresh rate, and performing a refresh on a second portion of the DRAM at a second refresh rate. The second portion includes one or more rows of the DRAM which do not meet a data retention criteria at the first refresh rate, and the second refresh rate is greater than the first refresh rate.

Abstract: A system has a first plurality of cores in a first coherency group. Each core transfers data in packets. The cores are directly coupled serially to form a serial path. The data packets are transferred along the serial path. The serial path is coupled at one end to a packet switch. The packet switch is coupled to a memory. The first plurality of cores and the packet switch are on an integrated circuit. The memory may or may not be on the integrated circuit. In another aspect a second plurality of cores in a second coherency group is coupled to the packet switch. The cores of the first and second pluralities may be reconfigured to form or become part of coherency groups different from the first and second coherency groups.

Abstract: A method for refreshing a Dynamic Random Access Memory (DRAM) includes performing a refresh on at least a portion of the DRAM at a first refresh rate, and performing a refresh on a second portion of the DRAM at a second refresh rate. The second portion includes one or more rows of the DRAM which do not meet a data retention criteria at the first refresh rate, and the second refresh rate is greater than the first refresh rate.

Abstract: A method for refreshing a Dynamic Random Access Memory (DRAM) includes performing a refresh on at least a portion of the DRAM at a first refresh rate, and performing a refresh on a second portion of the DRAM at a second refresh rate. The second portion includes one or more rows of the DRAM which do not meet a data retention criteria at the first refresh rate, and the second refresh rate is greater than the first refresh rate.

Abstract: A system has a first plurality of cores in a first coherency group. Each core transfers data in packets. The cores are directly coupled serially to form a serial path. The data packets are transferred along the serial path. The serial path is coupled at one end to a packet switch. The packet switch is coupled to a memory. The first plurality of cores and the packet switch are on an integrated circuit. The memory may or may not be on the integrated circuit. In another aspect a second plurality of cores in a second coherency group is coupled to the packet switch. The cores of the first and second pluralities may be reconfigured to form or become part of coherency groups different from the first and second coherency groups.

Abstract: A system has a first plurality of cores in a first coherency group. Each core transfers data in packets. The cores are directly coupled serially to form a serial path. The data packets are transferred along the serial path. The serial path is coupled at one end to a packet switch. The packet switch is coupled to a memory. The first plurality of cores and the packet switch are on an integrated circuit. The memory may or may not be on the integrated circuit. In another aspect a second plurality of cores in a second coherency group is coupled to the packet switch. The cores of the first and second pluralities may be reconfigured to form or become part of coherency groups different from the first and second coherency groups.

Abstract: A method for refreshing a Dynamic Random Access Memory (DRAM) includes performing a refresh on at least a portion of the DRAM at a first refresh rate, and performing a refresh on a second portion of the DRAM at a second refresh rate. The second portion includes one or more rows of the DRAM which do not meet a data retention criteria at the first refresh rate, and the second refresh rate is greater than the first refresh rate.

Abstract: A method is provided for error correction of a memory. The method includes: providing a first memory and a second memory; initiating a read operation of the first memory to retrieve data; performing an error correction code (ECC) processing on the data, wherein the ECC processing for determining that at least a portion of the data is erroneous and for providing corrected data; and determining if an address of the erroneous data is stored in the second memory, if the address of the erroneous data is stored in the second memory, storing the corrected data in the second memory, and if the address of the erroneous data is not stored in the second memory, storing the address in the second memory.

Abstract: A system has a first plurality of cores in a first coherency group. Each core transfers data in packets. The cores are directly coupled serially to form a serial path. The data packets are transferred along the serial path. The serial path is coupled at one end to a packet switch. The packet switch is coupled to a memory. The first plurality of cores and the packet switch are on an integrated circuit. The memory may or may not be on the integrated circuit. In another aspect a second plurality of cores in a second coherency group is coupled to the packet switch. The cores of the first and second pluralities may be reconfigured to form or become part of coherency groups different from the first and second coherency groups.

Abstract: A double-rate memory has an array of single word line memory cells arranged in rows and columns. The single word line memory cells provide and store data via a first port. Addressing and control circuitry is coupled to the array of single word line memory cells. The addressing and control circuitry receives an address enable signal to initiate an access of the array whereby an address is received, decoded, and corresponding data retrieved or stored. Edge detection circuitry receives a memory clock and provides the address enable signal upon each rising edge and each falling edge of the memory clock to perform two memory operations in a single cycle of the memory clock. A memory operation includes addressing the memory and storing data in the memory or retrieving and latching data from the memory. In another form a double-rate dual port memory permits two independent read/write memory accesses in a single memory cycle.

Abstract: A level shifting circuit having a signal input that operates in a first voltage domain and a signal output that operates in a second voltage domain. In some embodiments, the level shifting circuit includes a clocked level shifter. In some embodiments, the level shifting circuit includes a level shifting latch that latches a translated output signal. In one example, the level shifting latch includes a latch portion and a stack of transistors with a transistor having a control electrode coupled to a clock input.

Abstract: A device includes a first combinatorial logic stage having a first input to receive a first data value, a second input to receive a bypass value and an output to provide one of a representation of the first data value or a first predetermined value based on the bypass value. The device further includes a latch stage having a first input to receive a second data value, a second input to receive the bypass value and an output to provide one of a latched representation of the second data value or a second predetermined value based on the bypass value. The device additionally includes a second combinatorial logic stage having a first input coupled to the output of the first combinatorial logic stage, a second input coupled to the output of the latch stage, and an output.