Patents by Inventor George P. McGill

George P. McGill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5440241
    Abstract: A method for probe testing and burning-in integrated circuits formed within dice or chips on a silicon wafer and then optionally either: (1) dicing the wafer into individual chips for shipment or (2) mating the wafer for shipment with a facing substrate having a temperature coefficient of expansion (TCE) matching the TCE of the wafer. Advantageously, the facing substrate is used for both probe and burn-in operations as well as being made a part of the wafer package in option No. 2 above where either the whole silicon wafer or a partial silicon wafer meeting threshold die requirements is to be shipped. In addition, probe and burn-in operations are carried out rapidly at high yields only after all integrated circuit manufacture has been completed.
    Type: Grant
    Filed: March 6, 1992
    Date of Patent: August 8, 1995
    Assignee: Micron Technology, Inc.
    Inventors: Jerrold L. King, Jerry M. Brooks, Warren M. Farnworth, George P. McGill
  • Patent number: 5145099
    Abstract: An improved system for the production of semiconductor devices is described. The invention incorporates conventional die attach and lead bond means into a simplified, common machine system. An independently mounted, computer-controlled, television camera system observes, monitors, and controls the operational steps of the die attach-lead bond process using a close loop process. The invention serves to increase throughout and yields while reducing variation of the finished product.
    Type: Grant
    Filed: November 4, 1991
    Date of Patent: September 8, 1992
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Warren M. Farnworth, George P. McGill
  • Patent number: 5140405
    Abstract: An semiconductor assembly includes at least one die having substantially planar first and second engagement surfaces and external edges which define a die shape. A base having an opening formed therein receives the die. The base opening has peripheral edges which define an opening shape and size which is complementary to the die external shape. The opening edges engage the die edges to spatially fix the die in a selected orientation in a plane parallel to the die first planar engagement surface. An interconnecting plate has at least one substantially planar engagement surface facing the first planar engagement surface of the die received within the base opening. At least one conductive pad on the plate planar engagement surface is spatially aligned or registered with a corresponding conductive pad on the first engagement surface of the die.
    Type: Grant
    Filed: March 29, 1991
    Date of Patent: August 18, 1992
    Assignee: Micron Technology, Inc.
    Inventors: Jerrold L. King, Jerry M. Brooks, Warren M. Farnworth, George P. McGill
  • Patent number: 5062565
    Abstract: An improved system for the production of semiconductor devices is described. The invention incorporates conventional die attach and wire bond means into a simplified, common machine system. An independently mounted, computer-controlled, television camera system observes, monitors, and controls the operational steps of the die attach wire bond process using a close loop process. The invention serves to increase throughput and yields while reducing variation of the finished product.
    Type: Grant
    Filed: July 13, 1990
    Date of Patent: November 5, 1991
    Assignee: Micron Technology, Inc.
    Inventors: Alan G. Wood, Warren M. Farnworth, George P. McGill