Abstract: A clocked IGFET serial decoder circuit has a precharge transistor with its conduction channel connected between a V.sub.DD supply and an output terminal, a string of transistors with their conduction channels connected in series between the output terminal and a switch ground node and a ground switch transistor with its conduction channel connected between the switch ground node and a V.sub.SS supply. The gates of the transistors of the string receive input signals from clocked input buffers which bias the gates at V.sub.DD during the precharge interval when the precharge transistor is ON and the ground switch transistor is OFF. This allows the parasitic capacitances at the junctures of the transistors in the string to become substantially charged during the precharge interval and thus prevent rapid charge sharing at the output terminal when the circuit is enabled.

Abstract: A clocked IGFET logic circuit comprises a precharge transistor having its channel connected between a V.sub.DD supply terminal and an output terminal, a functional network connected between the output terminal and a switch ground node, the network containing a plurality of transistors each having its gates connected to receive a respective one of a plurality of input signals and its channel connected together with those of the other transistors of the functional network in a configuration which provides the circuit with a predetermined logical function, and a ground switch transistor having its channel connected between the switch ground node and a V.sub.SS supply terminal. The gate of the ground switch transistor receives a clock signal which turns that transistor OFF during a precharge phase of the clock signal and ON during an active phase of the clock signal.