Patents by Inventor George P. Zampetti

George P. Zampetti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7535931
    Abstract: A two-way time transfer protocol includes: sending a signal from a first node including a first clock and a first time interval counter coupled to the first clock over a transport physical layer coupled to the first node to a second node coupled to the transport physical layer, the second node including a second clock and a second time interval counter coupled to the second clock; then sending a last second node time interval counter value from the second time interval counter of the second node over the transport physical layer to the first node; and then comparing at the first node a last first node time interval counter value to the last second node time interval counter value. A first-way path latency from the first node to the second node is substantially equal to a second-way path latency from the second node to the first node, and all of a first node transmit delay, a first node receive delay, a second node transmit delay and a second node receive delay are substantially constant.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: May 19, 2009
    Assignee: Symmetricom, Inc.
    Inventors: George P. Zampetti, Robert P. Hamilton
  • Publication number: 20030094982
    Abstract: Systems and methods are described for a core sync module. A method includes receiving a pair of input clock signals; utilizing a stratum clock state machine to control a multiplexer; utilizing the multiplexer to switch an input of a main clock between each of the pair of input clock signals; inducing a phase build-out activity; and transmitting an output clock signal. An apparatus includes a first input clock digital phase-locked loop; a second input clock digital phase-locked loop; a stratum clock state machine coupled to the first input clock digital phase-locked loop and to the second input clock digital phase-locked loop; and a main clock phase-locked loop coupled to the first input clock digital phase-locked loop, to the second input clock digital phase-locked and to the stratum clock state machine.
    Type: Application
    Filed: November 20, 2001
    Publication date: May 22, 2003
    Inventors: George P. Zampetti, Robert Hamilton
  • Patent number: 6166608
    Abstract: The present invention is a stabilized oscillator system comprising an oven controlled crystal oscillator positioned inside an insulated housing. Within the insulated housing, there is a cold plate in thermal contact with the oven controlled crystal oscillator and a thermo-electric cooler in contact with the cold plate. A heat sink external to the insulated housing is in thermal contact with the thermo-electric cooler. The thermo-electric cooler pumps heat into or out of the oven controlled crystal oscillator through the cold plate and into or out of the heat sink. The thermo-electric cooler is controlled as part of a feedback loop which attempts to stabilize the output frequency of the oven controlled crystal oscillator.
    Type: Grant
    Filed: October 21, 1998
    Date of Patent: December 26, 2000
    Assignee: Symmetricom, Inc.
    Inventors: Morley M. Merriss, George P. Zampetti
  • Patent number: 5646519
    Abstract: A digital phase detector composed of: a digitally controllable signal delay device having a signal input, a signal output and a control input, the delay device being operative for conducting a signal from the signal input to the signal output with a time delay having a duration determined by a control signal supplied to the control input, the signal input being connected to receive either an input signal or a digital local clock signal; a phase relation detector connected to receive a first input signal from the signal output of the signal delay device and a second input signal constituted by the one of the input signal and the digital local clock signal which is not received by the signal input of the signal delay device, for periodically comparing the phases of the first and second input signals and for producing a binary output signal composed of a succession of signal segments, each segment having a first value when the first input signal is leading the second input signal in phase and a second value when
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: July 8, 1997
    Assignee: Symmetricom, Inc.
    Inventors: Michael M. Hamilton, Morley M. Merriss, George P. Zampetti