Patents by Inventor George Papasouliotis

George Papasouliotis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9806183
    Abstract: Methods for stress control in thin silicon (Si) wafer-based semiconductor materials. By a specific interrelation of process parameters (e.g., temperature, reactant supply, time), a highly uniform nucleation layer is formed on the Si substrate that mitigates and/or better controls the stress (tensile and compressive) in subsequent layers formed on the thin Si substrate.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: October 31, 2017
    Assignee: Veeco Instruments, Inc.
    Inventors: Jie Su, George Papasouliotis
  • Patent number: 9748113
    Abstract: Embodiments include systems and methods for producing semiconductor wafers having reduced quantities of point defects. These systems and methods include a tunable ultraviolet (UV) light source, which is controlled to produce a raster of a UV light beam across a surface of a semiconductor wafer during epitaxial growth to dissociate point defects in the semiconductor wafer. In various embodiments, the tunable UV light source is configured external to a Metal Organic Chemical Vapor Deposition (MOCVD) chamber and controlled such that the UV light beam is directed though a window defined in a wall of the MOCVD chamber.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: August 29, 2017
    Assignee: Veeco Intruments Inc.
    Inventors: Eric Armour, George Papasouliotis, Daewon Kwon
  • Publication number: 20170154986
    Abstract: Methods for stress control in thin silicon (Si) wafer-based semiconductor materials. By a specific interrelation of process parameters (e.g., temperature, reactant supply, time), a highly uniform nucleation layer is formed on the Si substrate that mitigates and/or better controls the stress (tensile and compressive) in subsequent layers formed on the thin Si substrate.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 1, 2017
    Inventors: Jie Su, George Papasouliotis
  • Publication number: 20170067163
    Abstract: A chemical vapor deposition system is disclosed herein. The chemical vapor deposition system has a plurality of reaction chambers to operate independently in the growth of epitaxial layers on wafers within each of the reaction chambers for the purpose of reducing processing time while maintaining the quality necessary for the fabrication of high-performance semiconductor devices.
    Type: Application
    Filed: August 24, 2016
    Publication date: March 9, 2017
    Inventors: George Papasouliotis, Miguel Saldana, Brett Snowden, Yuliy Rashkovsky, Michael Pacier
  • Publication number: 20170032974
    Abstract: Embodiments include systems and methods for producing semiconductor wafers having reduced quantities of point defects. These systems and methods include a tunable ultraviolet (UV) light source, which is controlled to produce a raster of a UV light beam across a surface of a semiconductor wafer during epitaxial growth to dissociate point defects in the semiconductor wafer. In various embodiments, the tunable UV light source is configured external to a Metal Organic Chemical Vapor Deposition (MOCVD) chamber and controlled such that the UV light beam is directed though a window defined in a wall of the MOCVD chamber.
    Type: Application
    Filed: July 30, 2015
    Publication date: February 2, 2017
    Inventors: Eric Armour, George Papasouliotis, Daewon Kwon
  • Publication number: 20160359004
    Abstract: Stress control using superlattice structures for epitaxy on base wafer substrates, including AlN/GaN superlattices for epitaxy of GaN on silicon {111} substrates. Crack-free GaN cap layers can be grown over superlattice structures containing AlN/GaN superlattice layers. Compressive and tensile stress can be precisely adjusted by changing the thickness of the superlattice layers and the number of superlattice layers. For a constant period thickness, growth conditions, such as growth rate of GaN, V/III ratio during AlN growth, and growth temperature, can be adjusted.
    Type: Application
    Filed: June 3, 2015
    Publication date: December 8, 2016
    Inventors: Jie Su, George Papasouliotis, Balakrishnan Krishnan, Soo Min Lee
  • Patent number: 8858816
    Abstract: A plasma processing tool is used to deposit material on a workpiece. For example, a method for conformal deposition of material is disclosed. In this embodiment, the plasma sheath shape is modified to allow material to impact the workpiece at a range of incident angles. By varying this range of incident angles over time, a variety of different features can be deposited onto. In another embodiment, a plasma processing tool is used to etch a workpiece. In this embodiment, the plasma sheath shape is altered to allow ions to impact the workpiece at a range of incident angles. By varying this range of incident angles over time, a variety of differently shaped features can be created.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: October 14, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ludovic Godet, Timothy Miller, George Papasouliotis, Vikram Singh
  • Patent number: 8728587
    Abstract: A plasma processing apparatus and method are disclosed which improve the repeatability of various plasma processes. The actual implanted dose is a function of implant conditions, as well as various other parameters. This method used knowledge of current implant conditions, as well as information about historical data to improve repeatability. In one embodiment, a plasma is created, a first sensing system is used to monitor a composition of the plasma and a second sensing system is used to monitor a total number of ions implanted. Information about plasma composition and dose per pulse is used to control one or more operating parameters in the plasma chamber. In another embodiment, this information is combined with historical data to control one or more operating parameters in the plasma chamber. In another embodiment, the thickness of material on the walls is measured, and used to modify one or more operating parameters.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: May 20, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: George Papasouliotis, Deven M. Raj, Harold Persing
  • Publication number: 20140034611
    Abstract: A plasma processing tool is used to deposit material on a workpiece. For example, a method for conformal deposition of material is disclosed. In this embodiment, the plasma sheath shape is modified to allow material to impact the workpiece at a range of incident angles. By varying this range of incident angles over time, a variety of different features can be deposited onto. In another embodiment, a plasma processing tool is used to etch a workpiece. In this embodiment, the plasma sheath shape is altered to allow ions to impact the workpiece at a range of incident angles. By varying this range of incident angles over time, a variety of differently shaped features can be created.
    Type: Application
    Filed: October 16, 2013
    Publication date: February 6, 2014
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Ludovic Godet, Timothy Miller, George Papasouliotis, Vikram Singh
  • Patent number: 8603591
    Abstract: A plasma processing tool is used to deposit material on a workpiece. For example, a method for conformal deposition of material is disclosed. In this embodiment, the plasma sheath shape is modified to allow material to impact the workpiece at a range of incident angles. By varying this range of incident angles over time, a variety of different features can be deposited onto. In another embodiment, a plasma processing tool is used to etch a workpiece. In this embodiment, the plasma sheath shape is altered to allow ions to impact the workpiece at a range of incident angles. By varying this range of incident angles over time, a variety of differently shaped features can be created.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: December 10, 2013
    Assignee: Varian Semiconductor Ewuipment Associates, Inc.
    Inventors: Ludovic Godet, Timothy Miller, George Papasouliotis, Vikram Singh
  • Patent number: 8431495
    Abstract: An apparatus and method are provided which allow the low cost patterned deposition of material onto a workpiece. A stencil mask, having chamfered edges is applied to the surface of the workpiece. The material is then deposited onto the workpiece, such as by PECVD. Because of the chamfered edges, the material thickness is much more uniform than is possible with traditional stencil masks. Stencil masks having a variety of cross sectional patterns are disclosed which improve deposition uniformity.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: April 30, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Helen Maynard, George Papasouliotis
  • Publication number: 20120328771
    Abstract: A plasma processing apparatus and method are disclosed which improve the repeatability of various plasma processes. The actual implanted dose is a function of implant conditions, as well as various other parameters. This method used knowledge of current implant conditions, as well as information about historical data to improve repeatability. In one embodiment, information about plasma composition and dose per pulse is used to control one or more operating parameters in the plasma chamber. In another embodiment, this information is combined with historical data to control one or more operating parameters in the plasma chamber.
    Type: Application
    Filed: June 24, 2011
    Publication date: December 27, 2012
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: George Papasouliotis, Deven Raj, Harold Persing
  • Publication number: 20100252531
    Abstract: A plasma processing tool is used to deposit material on a workpiece. For example, a method for conformal deposition of material is disclosed. In this embodiment, the plasma sheath shape is modified to allow material to impact the workpiece at a range of incident angles. By varying this range of incident angles over time, a variety of different features can be deposited onto. In another embodiment, a plasma processing tool is used to etch a workpiece. In this embodiment, the plasma sheath shape is altered to allow ions to impact the workpiece at a range of incident angles. By varying this range of incident angles over time, a variety of differently shaped features can be created.
    Type: Application
    Filed: December 23, 2009
    Publication date: October 7, 2010
    Inventors: Ludovic Godet, Timothy Miller, George Papasouliotis, Vikram Singh
  • Publication number: 20100098851
    Abstract: Techniques for atomic layer deposition (ALD) are disclosed. In one particular exemplary embodiment, the techniques may be realized as a system for ALD comprising a plurality of reactors in a stacked configuration, wherein each reactor comprises a wafer holding portion for holding a target wafer, a gas assembly coupled to the plurality of reactors and configured to provide at least one gas to at least one of the plurality of reactors, and an exhaust assembly coupled to the plurality of reactors and configured to exhaust the at least one gas from the at least one of the plurality of reactors. The gas assembly may further comprise a valve assembly coupled to each of the first gas inlet, the second gas inlet, and the third gas inlet, where the valve assembly is configured to selectively release at least one of the first gas, the second gas, and the third gas.
    Type: Application
    Filed: October 20, 2008
    Publication date: April 22, 2010
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Shigemi MURAKAWA, Vikram Singh, George Papasouliotis, Joseph C. Olson, Paul J. Murphy, Gary E. Dickerson
  • Publication number: 20090227061
    Abstract: Methods of controlling the diffusion of a dopant in a solar cell are disclosed. A second species is used in conjunction with the dopant to modify the diffusion region. For example, phosphorus and boron both diffuse by pairing with interstitial silicon atoms. Thus, by controlling the creation and location of these interstitials, the diffusion rate of the dopant can be controlled. In one embodiment, a heavier element, such as germanium, argon or silicon, is used to create interstitials. Because of the presence of these heavier elements, the dopant diffuses deeper into the substrate. In another embodiment, carbon is implanted. Carbon reduces the number of interstitials, and thus can be used to limit the diffusion of the dopant. In another embodiment, a lighter element, such as helium is used to amorphize the substrate. The crystalline-amorphous interface created limits diffusion of the dopant into the substrate.
    Type: Application
    Filed: March 4, 2009
    Publication date: September 10, 2009
    Inventors: Nicholas Bateman, Atul Gupta, Christopher Hatem, George Papasouliotis, Helen Maynard
  • Patent number: 7586100
    Abstract: A method of controlling a plasma doping process using a time-of-flight ion detector includes generating a plasma comprising dopant ions in a plasma chamber proximate to a platen supporting a substrate. The platen is biased with a bias voltage waveform having a negative potential that attracts ions in the plasma to the substrate for plasma doping. A spectrum of ions present in the plasma is measured as a function of ion mass with a time-of-flight ion detector. The total number ions impacting the substrate is measured with a Faraday dosimetry system. An implant profile is determined from the measured spectrum of ions. An integrated dose is determined from the measured total number of ions and the calculated implant profile. At least one plasma doping parameter is modified in response to the calculated integrated dose.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: September 8, 2009
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Deven M. Raj, Ludovic Godet, Bernard Lindsay, Timothy Miller, George Papasouliotis
  • Publication number: 20070224840
    Abstract: A method of selecting plasma doping process parameters includes determining a recipe parameter database for achieving at least one plasma doping condition. The initial recipe parameters are determined from the recipe parameter database. In-situ measurements of at least one plasma doping condition are performed. The in-situ measurements of the at least one plasma doping condition are correlated to at least one plasma doping result. At least one recipe parameter is changed in response to the correlation so as to improve at least one plasma doping process performance metric.
    Type: Application
    Filed: March 19, 2007
    Publication date: September 27, 2007
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Anthony Renau, Vikram Singh, Atul Gupta, Timothy Miller, Edwin Arevalo, George Papasouliotis, Yong Bae Jeon
  • Publication number: 20070087581
    Abstract: A technique for atomic layer deposition is disclosed. In one particular exemplary embodiment, the technique may be realized by a method for forming a strained thin film. The method may comprise supplying a substrate surface with one or more precursor substances having atoms of at least one first species and atoms of at least one second species, thereby forming a layer of the precursor substance on the substrate surface. The method may also comprise exposing the substrate surface to plasma-generated metastable atoms of a third species, wherein the metastable atoms desorb the atoms of the at least one second species from the substrate surface to form an atomic layer of the at least one first species. A desired amount of stress in the atomic layer of the at least one first species may be achieved by controlling one or more parameters in the atomic layer deposition process.
    Type: Application
    Filed: December 8, 2006
    Publication date: April 19, 2007
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Vikram SINGH, Harold Persing, Edmund Winder, Anthony Renau, George Papasouliotis