Abstract: Apparatus and method for performing low-latency multi-job submission via a single job descriptor is described herein. An apparatus embodiment includes a plurality of descriptor queues to stores job descriptors describing work to be performed and enqueue circuitry to receive a first job descriptor which includes a first field to store a Single Instruction Multiple Data (SIMD) width. If the SIMD width indicates that the first job descriptor is an SIMD job descriptor and open slots are available in the descriptor queues to store new job descriptors, then the enqueue circuitry is to generate a plurality of job descriptors based on fields of the first job descriptor and to store them in the open slots of the descriptor queues. The generated job descriptors are processed by processing pipelines to perform the work described. At least some of the generated job descriptors are processed concurrently or in parallel by different processing pipelines.

Abstract: A lossless data compressor of an aspect includes a first lossless data compressor circuitry coupled to receive input data. The first lossless data compressor circuitry is to apply a first lossless data compression approach to compress the input data to generate intermediate compressed data. The apparatus also includes a second lossless data compressor circuitry coupled with the first lossless data compressor circuitry to receive the intermediate compressed data. The second lossless data compressor circuitry is to apply a second lossless data compression approach to compress at least some of the intermediate compressed data to generate compressed data. The second lossless data compression approach different than the first lossless data compression approach. Lossless data decompressors are also disclosed, as are methods of lossless data compression and decompression.

Abstract: Systems, methods, and apparatuses to low-latency page decompression and compression acceleration are described. In one embodiment, a system on a chip (SoC) includes a hardware processor core, and an accelerator circuit coupled to the hardware processor core, the accelerator circuit comprising a decompressor circuit and a direct memory access circuit to: in response to a first descriptor sent from the hardware processor core, cause the decompressor circuit to decompress compressed data from the direct memory access circuit into decompressed data and store the decompressed data in a buffer in the accelerator circuit, and in response to a second descriptor sent from the hardware processor core separately from the first descriptor, cause the decompressed data to be written from the buffer to memory external to the accelerator circuit by the direct memory access circuit.

Abstract: An embodiment of an integrated circuit may comprise, coupled to a core, hardware decompression accelerators, a compressed cache, a processor communicatively coupled to the hardware decompression accelerators and the compressed cache, and memory communicatively coupled to the processor, wherein the memory stores microcode instructions that when executed by the processor causes the processor to load a page table entry in response to an indication of a page fault, determine if the page table entry indicates that the page is to be decompressed on fault, and, if so determined, modify a first decompression work descriptor at a first address and a second decompression work descriptor at a second address based on information from the page table entry, and generate a first enqueue transaction to the hardware decompression accelerators with the first address of the first decompression work descriptor and a second enqueue transaction to the hardware decompression accelerators with the second address of the second decomp

Abstract: Apparatus and method for performing low-latency multi-job submission via a single job descriptor is described herein. An apparatus embodiment includes a plurality of descriptor queues to stores job descriptors describing work to be performed and enqueue circuitry to receive a first job descriptor which includes a first field to store a Single Instruction Multiple Data (SIMD) width. If the SIMD width indicates that the first job descriptor is an SIMD job descriptor and open slots are available in the descriptor queues to store new job descriptors, then the enqueue circuitry is to generate a plurality of job descriptors based on fields of the first job descriptor and to store them in the open slots of the descriptor queues. The generated job descriptors are processed by processing pipelines to perform the work described. At least some of the generated job descriptors are processed concurrently or in parallel by different processing pipelines.

Abstract: A lossless data compressor of an aspect includes a first lossless data compressor circuitry coupled to receive input data. The first lossless data compressor circuitry is to apply a first lossless data compression approach to compress the input data to generate intermediate compressed data. The apparatus also includes a second lossless data compressor circuitry coupled with the first lossless data compressor circuitry to receive the intermediate compressed data. The second lossless data compressor circuitry is to apply a second lossless data compression approach to compress at least some of the intermediate compressed data to generate compressed data. The second lossless data compression approach different than the first lossless data compression approach. Lossless data decompressors are also disclosed, as are methods of lossless data compression and decompression.

Abstract: Hardware accelerators and methods for out-of-order processing are described. In one embodiment, a processor includes a hardware accelerator having a plurality of processing elements coupled to form a plurality of logical rows of a multidimensional processing array and a plurality of logical columns of the multidimensional processing array, wherein a processing element of the plurality of processing elements includes a switch to selectively source, from either of an output for a first dataset from an upstream processing element of the plurality of processing elements or a boundary condition value for a second dataset stored in the processing element, based on a switch control value provided to the processing element; and a core coupled to the hardware accelerator.

Abstract: Hardware accelerators and methods for out-of-order processing are described. In one embodiment, a processor includes a hardware accelerator having a plurality of processing elements coupled to form a plurality of logical rows of a multidimensional processing array and a plurality of logical columns of the multidimensional processing array, wherein a processing element of the plurality of processing elements includes a switch to selectively source, from either of an output for a first dataset from an upstream processing element of the plurality of processing elements or a boundary condition value for a second dataset stored in the processing element, based on a switch control value provided to the processing element; and a core coupled to the hardware accelerator.

Abstract: According to some embodiments, a system provides acquisition of a first sample of a data signal based on a first clock signal associated with a first phase, the first sample associated with a first data eye of a clock cycle, acquisition of a second sample of the data signal based on a second clock signal associated with a second phase, the second sample associated with a second data eye of the clock cycle, determination of whether the first sample reflects expected data associated with the first data eye, control of the first phase of the first clock signal based on whether the first sample reflects the expected data associated with the first data eye, determination of whether the second sample reflects expected data associated with the second data eye, and control of the second phase of the second clock signal based on whether the second sample reflects the expected data associated with the second data eye.

Abstract: A method, apparatus and system for use in determining a pilot-to-data power ratio by receiving a data symbol (122) having a data amplitude, receiving a pilot signal (124) having a pilot amplitude, reverse training (350) an automatic gain (154) based on the data amplitude and the pilot amplitude, and determining a pilot-to-data power ratio (250) according to the reverse training of the automatic gain. In some embodiments the method further compensates for channel fading in the data symbol by providing for channel correction (340) on the data symbol, providing for channel correction (344) on the pilot signal and dividing the channel corrected data symbol by the channel corrected pilot signal providing a fading compensated data symbol, where the fading compensated data symbol (150) is provided prior to reverse training such that the reverse training is based at least in part on the fading compensated data symbol.

Abstract: A method, apparatus and system for use in determining a pilot-to-data power ratio by receiving a data symbol (122) having a data amplitude, receiving a pilot signal (124) having a pilot amplitude, reverse training (350) an automatic gain (154) based on the data amplitude and the pilot amplitude, and determining a pilot-to-data power ratio (250) according to the reverse training of the automatic gain. In some embodiments the method further compensates for channel fading in the data symbol by providing for channel correction (340) on the data symbol, providing for channel correction (344) on the pilot signal and dividing the channel corrected data symbol by the channel corrected pilot signal providing a fading compensated data symbol, where the fading compensated data symbol (150) is provided prior to reverse training such that the reverse training is based at least in part on the fading compensated data symbol.