Abstract: An improvement in the margining circuit wherein a variable load is provided to a column of EPROM cells. A plurality of parallel transistors are coupled as the load and by controlling the number of transistors which are turned on, the voltage to the column can be adjusted, effectively adjusting the current to the cells.

Abstract: A cell employing floating gate storage device particularly suited for neural networks. The floating gate from the floating gate device extends to and becomes part of a second, field effect device. Current through the second device is affected by the charge on the floating gate. The weighting factor for the cell is determined by the amount of charge on the floating gate. By charging the floating gate to various levels, a continuum of weighting factors is obtained. Multiplication is obtained since the current through the second device is a function of the weighting factor.

Abstract: An EPROM includes an on chip circuitry for selecting an alternative chapter mode addressing scheme. By utilizing the chapter addressing mode, a plurality of devices can be coupled in parallel, wherein each device is treated as a chapter of the total memory capacity. Hard latches are used to store a designated code and soft latches are used to latch in chapter addresses from data lines. A chapter is evaluated if values stored in the hard latch match the values inputted to the soft latch.

Abstract: An EPROM which includes on-chip circuitry for selecting alternate addressing. An EPROM cell, separate from the memory's array, is programmed to convert the memory to the alternate page mode addressing. The selection of the pages is done through the data lines. This frees address lines when the alternate mode is selected.