Patents by Inventor George R. Hayek
George R. Hayek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9723342Abstract: An approach is provided for determining a program clock reference (PCR) value validity, for avoiding inaccurate variable delay reference (VDR) values, and for avoiding a mismatch in a data packet between a sequence number and a packet number for a wireless display extension. The approach involves determining to generate a data packet carrier having an optional PCR value, a VDR) value, and a validity indicator. The approach may further involve processing the data packet carrier to determine whether the data packet carrier has the optional PCR value. The approach may also involve causing, at least in part, a surrogate PCR value to be generated based, at least in part, on a determined absence of the optional PCR value from the data packet carrier.Type: GrantFiled: December 21, 2011Date of Patent: August 1, 2017Assignee: Intel CorporationInventors: Guoqing Li, Joseph A. Bennett, Gideon Prat, Solomon B. Trainin, Sang-Hee Lee, Vallabhajosyula Z. Somayazulu, George R. Hayek, Pat Brouillette, Dmitrii A. Loukianov
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Publication number: 20150382035Abstract: An approach is provided for determining a program clock reference (PCR) value validity, for avoiding inaccurate variable delay reference (VDR) values, and for avoiding a mismatch in a data packet between a sequence number and a packet number for a wireless display extension. The approach involves determining to generate a data packet carrier having an optional PCR value, a VDR) value, and a validity indicator. The approach may further involve processing the data packet carrier to determine whether the data packet carrier has the optional PCR value. The approach may also involve causing, at least in part, a surrogate PCR value to be generated based, at least in part, on a determined absence of the optional PCR value from the data packet carrier.Type: ApplicationFiled: December 21, 2011Publication date: December 31, 2015Inventors: Guoqing Li, Joseph A. Bennett, Gideon Prat, Solomon B. Trainin, Sang-Hee Lee, Vallabhajosyula Z. Somayazulu, George R. Hayek, Pat Brouillette, Dmitrii A. Loukianov
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Patent number: 9052902Abstract: Techniques are described to transmit commands to a display device. The commands can be transmitted in header byte fields of secondary data packets. The commands can be used to cause a target device to capture a frame, enter or exit self refresh mode, or reduce power use of a connection. In addition, a request to exit main link standby mode can cause the target enter training mode without explicit command to exit main link standby mode.Type: GrantFiled: September 24, 2010Date of Patent: June 9, 2015Assignee: Intel CorporationInventors: George R. Hayek, Todd M. Witter, Seh W. Kwa, Maximino Vasquez
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Publication number: 20150113308Abstract: Techniques are described to transmit commands to a display device. The commands can be transmitted in header byte fields of secondary data packets. The commands can be used to cause a target device to capture a frame, enter or exit self refresh mode, or reduce power use of a connection. In addition, a request to exit main link standby mode can cause the target enter training mode without explicit command to exit main link standby mode.Type: ApplicationFiled: December 22, 2014Publication date: April 23, 2015Applicant: INTEL CORPORATIONInventors: George R. Hayek, Todd M. Witter, Seh W. Kwa, Maximino Vasquez
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Publication number: 20150085187Abstract: An electronic device, method, and at least one machine readable medium for burst mode processing of video data with inband link power management are provided herein. The method includes receiving a pixel stream, transferring the received stream as currently-available frame-formatted video data to a sink in burst at high data rate, and entering a reduced-power operating state until transfer of additional currently-available video data is enabled. The method may include issuing inband command signals to cause the link to enter into and exit from the reduced-power link operating states.Type: ApplicationFiled: September 20, 2013Publication date: March 26, 2015Inventors: Huimin Chen, George R. Hayek, Robert Jamie Johnston, Pravas Pradhan, Satyanarayana Avadhanam, Seh W. Kwa
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Patent number: 8856842Abstract: In a wireless video system, the clock rate for wirelessly transmitting the video data from the transmitting device should be identical to the clock rate for receiving the video data at the receiving device. But the two devices have separate clocks, whose frequencies may drift apart over time, leading the video buffer to be over run or under run. Clock synchronizing messages to prevent this may be sent at short intervals when clock synchronization is first being acquired, and at larger intervals after clock synchronization has already been achieved and is merely being maintained.Type: GrantFiled: December 6, 2012Date of Patent: October 7, 2014Assignee: Intel CorporationInventors: Guoqing C. Li, Etan Shirron, Yaniv Frishman, George R. Hayek
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Publication number: 20140241380Abstract: A data packet or payload defined by a first format, is generated and is wrapped with headers as defined by a second format, and is processed through a pass through mechanism for transmission based on the second format. The processing includes adding or encapsulating the payload in the transmission data packet. When receiving the transmitted data packet, the headers may be parsed, and the payload processed.Type: ApplicationFiled: November 17, 2011Publication date: August 28, 2014Inventors: Joseph A. Bennett, Guoging Li, Vallabhajosyula S. Somayazulu, George R. Hayek, Gideon Prat, Srikanth Kambhatla
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Publication number: 20140086310Abstract: Described herein are techniques related to power efficient encoder architecture during static frame or sub-frame detection. In particular, a method of implementing a power savings algorithm is described upon detection of the static frame or sub-frame by the encoder architecture.Type: ApplicationFiled: September 21, 2012Publication date: March 27, 2014Inventors: Jason D. Tanner, Scott W. Cheng, George R. Hayek
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Publication number: 20130179929Abstract: In a wireless video system, the clock rate for wirelessly transmitting the video data from the transmitting device should be identical to the clock rate for receiving the video data at the receiving device. But the two devices have separate clocks, whose frequencies may drift apart over time, leading the video buffer to be over run or under run. Clock synchronizing messages to prevent this may be sent at short intervals when clock synchronization is first being acquired, and at larger intervals after clock synchronization has already been achieved and is merely being maintained.Type: ApplicationFiled: December 6, 2012Publication date: July 11, 2013Inventors: Guoqing C. Li, Etan Shirron, Yaniv Frishman, George R. Hayek
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Publication number: 20120079295Abstract: Techniques are described to transmit commands to a display device. The commands can be transmitted in header byte fields of secondary data packets. The commands can be used to cause a target device to capture a frame, enter or exit self refresh mode, or reduce power use of a connection. In addition, a request to exit main link standby mode can cause the target enter training mode without explicit command to exit main link standby mode.Type: ApplicationFiled: September 24, 2010Publication date: March 29, 2012Inventors: George R. Hayek, Todd M. Witter, Seh W. Kwa, Maximino Vasquez
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Patent number: 6317803Abstract: A high throughput memory access port is provided. The port includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The port allows memory read and write requests to be pipelined in order to hide the effects of memory access latency. In particular, the port allows bus transactions to be performed in either a non-pipelined mode, such as provided by PCI, or in a pipelined mode. In the pipelined mode, one or more additional memory access requests are permitted to be inserted between a first memory access request and its corresponding data transfer. In contrast, in the non-pipelined mode, an additional memory access request cannot be inserted between a first memory access request and its corresponding data transfer.Type: GrantFiled: September 27, 1996Date of Patent: November 13, 2001Assignee: Intel CorporationInventors: Norman J. Rasmussen, Gary A. Solomon, David G. Carson, George R. Hayek, Brent S. Baxter, Colyn Case
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Patent number: 6112284Abstract: A memory controller having a data strobe that tracks the column access strobe signal in a computer system having Extended Data Out (EDO) DRAMs. The data strobe signal follows, by a predetermined delay, the column access strobe signal, and therefore any skew in the column access strobe signal is inherently included within the data strobe signal. As a result, the data can be latched out, responsive to said data strobe signal, at approximately the center of the valid window.Type: GrantFiled: December 30, 1994Date of Patent: August 29, 2000Assignee: Intel CorporationInventors: George R. Hayek, Joe M. Nardone, Aniruddha Kundu, Kuljit S. Bains
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Patent number: 6097402Abstract: A method and system for enhancing graphics processing through selected placement of at least one graphics operand in main memory. The system includes a graphics controller in communication with system memory through a dedicated graphics bus such as an Accelerated Graphics Port (AGP) bus. This allows texture maps, alpha blending data and other graphics information to be contained in system memory without degradation of system performance.Type: GrantFiled: February 10, 1998Date of Patent: August 1, 2000Assignee: Intel CorporationInventors: Colyn Case, Brian K. Langendorf, George R. Hayek, Kim A. Meinerth
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Patent number: 5978952Abstract: Error correction circuitry attempts to detect and correct on the fly erroneous words within random access memory (RAM) within a computer system. RAM errors are scrubbed or corrected back in the memory without delaying the memory access cycle. Rather, the address of the section or row of RAM that contains the correctable error is latched for later used by an interrupt-driven firmware memory-error scrub routine. This routine reads and rewrites each word within the indicated memory section--the erroneous word is read, corrected on-the-fly as it is read, and then rewritten back into memory correctly. If the size of the memory section exceeds a predetermined threshold, then the process of reading and re-writing that section is divided into smaller sub-processes that are distributed in time using a delayed interrupt mechanism. Duration of each memory scrubbing subprocess is kept short enough that the response time of the computer system is not impaired with the housekeeping task of scrubbing RAM memory errors.Type: GrantFiled: December 31, 1996Date of Patent: November 2, 1999Assignee: Intel CorporationInventors: George R. Hayek, Radhakrishnan Venkataraman, Jasmin Ajanovic
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Patent number: 5978737Abstract: A system for detecting hazardous conditions during operation of a vehicle. In one embodiment, the system includes a plurality of sensors that monitor a plurality of conditions and transmit condition signals each representing a measure of a condition. A plurality of rate determination circuits is coupled to the sensors and continually receives the condition signals, wherein each rate determination circuit calculates rates of change for the condition, including a baseline rate of change, and outputs a potential hazard value representing a deviation of a rate of change from the baseline rate that exceeds a predetermined threshold value. An evaluation circuit receives the potential hazard value, calculates a new potential hazard value using the potential hazard value and a rate of change for at least one associated condition and determines whether an actual hazard exists by comparing the new potential hazard value with a stored value that corresponds to the condition.Type: GrantFiled: October 16, 1997Date of Patent: November 2, 1999Assignee: Intel CorporationInventors: Stephen S. Pawlowski, Andrew F. Glew, George R. Hayek, Harshvardhan P. Sharangpani, Richard C. Calderwood
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Patent number: 5918025Abstract: A method for converting signals from one arbitration and management protocol to another. The conversion is performed by at least three state machines. The conversion circuit converts a set of signals on the first bus to a bus request signal on the second bus. The conversion circuit also converts a signal from the second bus and a set of signals on the first bus to bus grant and memory acknowledge signals on the first bus.Type: GrantFiled: December 31, 1996Date of Patent: June 29, 1999Assignee: Intel CorporationInventors: George R. Hayek, Brian Langendorf, Jasmin Ajanovic, Rajeev K. Prasad
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Patent number: 5911051Abstract: A high throughput memory access interface is provided. The interface includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The interface allows memory access requests to be performed in such a manner that only portions of an access request are required to be transmitted to the target device for certain bus transactions. Each access request includes command bits, address bits, and length bits. In the initiating device, each access request is separated into three segments, which are stored in separate registers in both the initiating device and the target device. Only the segment which contains the lowest order address bits and the length bits is required by the target device to initiate the bus transaction. Thus, if either of the other two segments has not changed since the previous access request, then such segment or segments are not transmitted to the target.Type: GrantFiled: September 27, 1996Date of Patent: June 8, 1999Assignee: Intel CorporationInventors: David G. Carson, George R. Hayek, Brent S. Baxter, Colyn Case, Kim A. Meinerth, Brian K. Langendorf
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Patent number: 5740385Abstract: A bridge for coupling a host bus to a peripheral component interconnect (PCI) bus. A controller is used to transfer an address from the host bus while a datapath is used to transfer data from the host bus. The address and data is then transferred to the PCI bus over a set of signal lines coupled to the PCI bus such that each signal line transfers at least a portion of the address as well as at least a portion of data.Type: GrantFiled: December 19, 1994Date of Patent: April 14, 1998Assignee: Intel CorporationInventors: George R. Hayek, Brian K. Langendorf, Aniruddha Kundu, Kuljit S. Bains, Gary A. Solomon
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Patent number: 5640519Abstract: An arbitration circuit which controls arbitration for a resource by a first plurality of agents including a latency sensitive agent. The arbitration circuit comprises a mapping circuit and an arbiter. The mapping circuit is coupled to the first plurality of agents in order to receive a resource request signal from the latency sensitive agent and thereafter produce a plurality of request signals identical to the resource request signal. These request signals are input into at least a first and second I/O ports of the arbiter. The arbiter, which is coupled to the mapping circuit, including a second plurality of I/O ports and a second plurality of control ports each corresponding to one of the I/O ports. The arbiter is configured to arbitrate request signals input into the second plurality of I/O ports including the plurality of request signals, to monitor which I/O port was last activated, and to deactivate a control port associated with the I/O port thereby producing a control signal.Type: GrantFiled: September 15, 1995Date of Patent: June 17, 1997Assignee: Intel CorporationInventors: Brian K. Langendorf, James M. Dodd, George R. Hayek
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Patent number: 5625779Abstract: An arbitration signaling mechanism for an intermediate bus coupled between an expansion bridge and a host bridge that manages communication over the intermediate bus. The host bridge includes a CPU posting buffer for posting transactions between a CPU and the expansion bridge, and a DRAM buffer for storing data to be written into the DRAM. The host bridge also includes an arbiter coupled to receive a request signal from the expansion bridge and any other bus agents coupled to the expansion bridge. Responsive to a request from the expansion bridge, the arbiter empties the CPU posting buffer and the DRAM buffer before asserting an acknowledge signal. A passive release method is provided, which includes signaling a passive release semantic by the expansion bridge during a communication cycle in which the expansion bridge has bus control. The host bridge can grant temporary use of the bus to another bus agent before again granting access to the expansion bridge.Type: GrantFiled: December 30, 1994Date of Patent: April 29, 1997Assignee: Intel CorporationInventors: Gary A. Solomon, Peter D. MacWilliams, George R. Hayek, Nicholas D. Wade, Abid Asghar