Abstract: A random access memory circuit for use with positive and negative supply voltages, a read enable line, an output line, and write "1" and "0" lines includes first, second, third, and fourth level shifting diodes. A first input isolation diode is connected between the write "1" line and the first level shifting diode. A second input isolation diode is connected between the write "0" line and the cathode of the third level shifting diode. The drain of a first write FET is connected to the anode of the third diode, the source is connected to the read enable line, and the gate is connected to the cathode of the second level shifting diode. A second write FET has its drain connected to the anode of the first level shifting diode, its source connected to the read enable line, and its gate connected to the cathode of the fourth diode. An output buffer FET is connected by its source to the read enable line, by its gate to the cathode of the fourth diode.