Abstract: A method is disclosed for making gate oxides on a silicon wafer surface for multiple voltage applications comprising the steps of growing an oxide layer (12) on a wafer (10) surface, exposing the surface of the oxide layer (12) to a nitrogen ion containing plasma to form a nitrided layer (22). Next, a photoresist layer (14) is deposited over a portion of the oxide layer (12) and the isolation (30), followed by etching of the exposed nitrided layer 22 and a portion of the oxide layer (12) to create a thinner silicon dioxide layer (32). The photoresist layer (14) is removed, the wafer (10) is cleaned and then the thinner silicon dioxide layer (32) is removed prior to a final oxidation step to form a thinner silicon dioxide layer (34) having a different thickness than the silicon dioxide layer (12).

Abstract: A method is disclosed for making gate oxides on a silicon wafer surface for multiple voltage applications comprising the steps of growing an oxide layer (12) on a wafer (10) surface, exposing the surface of the oxide layer (12) to a nitrogen ion containing plasma to form a nitrided layer (22). Next, a photoresist layer (14) is deposited over a portion of the oxide layer (12) and the isolation (30), followed by etching of the exposed nitrided layer 22 and a portion of the oxide layer (12) to create a thinner silicon dioxide layer (32). The photoresist layer (14) is removed, the wafer (10) is cleaned and then the thinner silicon dioxide layer (32) is removed prior to a final oxidation step to form a thinner silicon dioxide layer (34) having a different thickness than the silicon dioxide layer (12).

Abstract: A method for fabricating a semiconductor resistor in embedded FLASH memory applications is described. In the method a gate stack (54) is formed on an insulating region (70) of a semiconductor substrate. The control gate (20) is removed from the gate stack (54) and electric contacts (125), (130) are formed to contact the floating gate (16) to form the resistor.

Abstract: A mixed voltage CMOS process for fabricating transistors with different source-drain profiles is described. The present invention comprises a method for manufacturing a CMOS integrated circuit with a low voltage device 24 and a high voltage device 26 comprising the steps of obtaining active regions in a substrate 10 with gates 30 and 32 for the low voltage device 24 and the high voltage device 26, respectively, obtaining lightly implanted source and drain extensions 38 and 40 for the low voltage device 24, forming a side wall 42, 44, 46 and 48 next to each gate 30 and 32, and angularly implanting each of the source and drain regions 52, 54, 56 and 58 with an impurity 50 of a selected type for both the low voltage device 24 and the high voltage device 26, to eliminate the need for separately implanting the first voltage device and second voltage device with different source-drain extensions.

Abstract: A method is disclosed for making gate oxides on a silicon wafer surface for multiple voltage applications comprising the steps of growing an oxide layer (12) on a wafer (10) surface. Next, a photoresist layer (14) is deposited over a portion of the oxide layer (12) and the isolation (30). The entire wafer (10) is exposed to a nitrogen ion containing plasma to form a nitrided layer (22). The photoresist (14) is removed, and the exposed portion of the oxide layer (12) is etched to the wafer (10) surface. Finally, an oxidation step forms a silicon dioxide layer (34) having a different thickness than the silicon dioxide layer (12).

Abstract: A method is disclosed of nitridating an oxide containing surface the disclosed method includes the steps of, obtaining a substrate, growing an oxide layer on the substrate, exposing the surface of the oxide layer to a nitrogen ion containing plasma at, e.g., room temperature, wherein the nitrogen ions form a nitrided layer on the oxide layer resistant to chemistries used to etch oxide.

Abstract: A method is disclosed of nitridating an oxide layer (12) to form a stop layer for selective etching of sacrificial layer comprising the steps of, obtaining a wafer (10), forming a gate (30) on the wafer (10), depositing an oxide layer (12) on the wafer (10) and the gate (30), exposing the surface of the oxide layer (12) to a nitrogen ion containing plasma at, e.g., room temperature, wherein the nitrogen ions form a nitrided layer (22) on the oxide layer (12). Next, a silicate layer (32) is deposited on the nitrided layer (22), planarized and patterned with photoresist (14) for etching. The contacts or vias are then formed through the silicate layer (32) by etching down to the nitrided layer (22) that acts as a stop layer, followed by a second etching step that removes the nitrided layer (22). The photoresist (14) is then stripped and the silicon oxide layer (12) etch down to the wafer (10).

Abstract: A method of forming silicided narrow (i.e., sub-0.25 .mu.m) polysilicon lines. A layer of titanium is deposited over a semiconductor body having polysilicon lines formed thereon Either before or after the titanium deposition and before the react step, an implant is performed using a gas that will not poison the subsequent silicidation reaction. Exemplary gases include the noble element gases such as argon, krypton, xenon, and neon. The titanium is then reacted with the polysilicon lines to form titanium silicide. The gas implant causes the C49 grain size of the titanium silicide to be reduced, which makes the transformation to the C54 phase easier. Finally, an anneal is performed to transform the titanium silicide from the C49 phase to the C54 phase.

Abstract: The invention comprises an integrated circuit having both low voltage and high voltage MOS transistors and a method for making the integrated circuit. In accordance with the method of making the integrated circuit, a first oxide layer is formed outwardly from a semiconductor substrate comprising a low voltage region and a high voltage region. A sacrificial layer is formed outwardly from the first oxide layer. The part of the sacrificial layer disposed outwardly from the low voltage region is removed to form an intermediate structure. The intermediate structure is selectively etched to remove the part of the first oxide layer disposed outwardly from the low voltage region. A second oxide layer is then formed comprising a first area disposed outwardly from the low voltage region and second area disposed outwardly from the high voltage region. The formation of the second oxide layer in the second area consumes the sacrificial layer.

Abstract: A capacitor and method of forming the capacitor for high density applications. The capacitor (100) comprises a storage node (106) having peaks (108) formed on a surface thereof. The peaks (108) are created by forming a photoresist residue layer (130) on the polysilicon layer of the storage node (108). The structure is then dry etched using the residue layer (130) as a mask to create peaks (108).

Abstract: A capacitor and method of forming the capacitor for high density applications. The capacitor (100) comprises a storage node (106) having waves (108) formed on the vertical surfaces thereof. The waves (108) are created using a silylated photoresist. The conditions of silylation and subsequent etch are such that, when etched, the silylated photoresist has waves on the vertical edges thereof. During the etch to form the storage node (106), the waves are transferred to the storage node (106). Waves (108) increase the surface area of the storage node (106) and thus the resulting capacitance.

Abstract: In a process for creating a mask on the surface of an integrated circuit workpiece, a first layer of resist is applied to the surface of the workpiece. An upper portion of this first layer is metallized. A second layer of photoresist is applied to the first layer. The second layer of photoresist is selectively exposed and developed. Using the developed second layer as a mask, exposed respective areas of the metallized upper portion of the first layer are etched, and the non-metallized portions of the first layer are subsequently etched. The result is a metallized mask on the surface of the workpiece that avoids the problems of high topographical relief and irradiation reflections from the workpiece surface.

Abstract: A process for silylation of positive or negative photosensitive resist layer on a semiconductor wafer after the resist layer has been exposed to radiant energy through a mask which includes introducing a silylating agent to the wafer at high pressure over 760 torr and, usually, at temperatures less than 180.degree. C. Increased pressure increases the rate of silylation, allows practical use of lower process temperatures, and, therefore, allows better process control. Also an apparatus is disclosed for applying the high pressure silylation process to a wafer.

Abstract: An electrical field-enhanced electron image projector (10) is exposed to an electrical field source (26) to induce the emission of electrons (20) which flow across a gap (28) from a pattern (14) of mask (12) to a photoresist layer (18) of a substrate (16). A heat source (22) can be applied to increase the flow of electrons (20) from the pattern (14) to the photoresist layer (18). As the gap (28) distance decreases, the ability of electrons (20) to move from the pattern (14) to the photoresist layer (18) increases.

Abstract: An electron image projector (10) is exposed to a heat source (22) to induce the emission of electrons (20) which flow from a pattern (14) of a mask (12) to a photoresist layer (18) of a substrate (16). An electron field (26) is applied across the substrate (16) and the mask (12) to accelerate the electrons (20) from the pattern (14) to the photoresist layer (18) to form a shape (24) on the photoresist layer (18) which reproduces the shape of the pattern (14). A projection system (28) can be disposed between the substrate (16) and the mask (12) to selectively direct the plurality of electrons (20) from the pattern (14) to the photoresist layer (18).