Abstract: The present invention is directed to a system having a shared processing resource, a plurality of processing modules and a synchronization control module. The shared processing resource is configured to perform processing operations in connection with input data provided by the processing modules, in response to a start indication. Each of the processing modules is configured to perform selected processing operations. At least one of the processing modules is configured to provide input data to the shared processing resource. Each processing module that provides input data is configured to generate a hold indication and to provide the input data to the shared processing resource in response to a synchronization barrier lock. Each processing module is configured to generate a start enable indication. Each processing module that provides input data generates a start enable indication after providing the input data.

Abstract: A system and method for circuitry design verification testing using a structure of interface independent classes to provide for rapid prototyping and design modification while maximizing test code re-use. A circuit simulation subsystem is interfaced with a test subsystem. The test subsystem employs a system transaction class for collecting common routines and pointers to device transactions. One or more configuration transaction classes derived from the system transaction class define transactions between functional models within the simulation subsystem and cause instantiation of the respective functional models. Operations are performed on the functional models via pointers to interface independent transaction classes which define interfaces to the devices. The operations are mapped to the current designs of the functional models by subclasses of the interface independent transaction classes.

Abstract: A system and method for circuitry design verification testing which provides for maximized code re-use without unnecessary allocation of system resources. A circuit simulation subsystem is interfaced with a test subsystem. The test subsystem employs a system transaction class which collects convenience routines and thereby maximizes code re-use. The system transaction class contains pointers to device transaction classes which correspond to each of the functional models in the simulation subsystem, but does not require instantiation of all of the device transaction classes and associated device objects. One or more configuration transaction classes derived from the system transaction class define transactions between selected ones of the functional models within the simulation subsystem. The configuration transaction classes inherit the convenience routines of the system transaction class, but cause instantiation of the respective functional models only when needed for a transaction.

Abstract: A diagnostic subsystem is used in a digital device in a digital computer system includes a diagnostic register, a device output control circuit and a diagnostic register reset circuit. The diagnostic register includes a plurality of stages each of which is associated with one of the types of transfers over the bus. Each stage is selectively conditionable by the digital computer system's processor. The device output control circuit controls transfers by the digital device over the bus. The device output control circuit enables the digital device, when it is to engage in a transfer, to transfer information correctly when the associated stage is set and to transfer information incorrectly when the stage has the set condition. For transfers in which the one device is to transmit information over the bus, the incorrectly transmitted information causes error checking circuitry in other devices in the system to generate error indications, which are provided to the processor.

Abstract: An interface subsystem for use in a system including one or more simulation systems facilitates simulation of one or more simulation models under control of one or more tests. The interface subsystem allows the tests and simulation systems to transfer information therebetween and enables said tests to control the simulation systems in simulating the simulation model during a simulation run. The simulation systems include transactors which provide information to the simulation model at the beginning of a simulation run, pause a simulation run in response to detection of a selected event, and generate simulation result information. The interface subsystem includes, associated with each test, a simulation information generator, a simulation control indicator generator, and a information receiver; associated with each simulation system an information receiver associated with each transactor and a simulator interface module; and an interface core.