Abstract: Methods, systems, and devices for adjustable column address scramble using fuses are described. A testing device may detect a first error in a first column plane of a memory array and a second error in a second column plane of the memory array. The testing device may identify a first column address of the first column plane associated with the first error and a second column address of the second column plane based on detecting the first error and the second error. The testing device may determine, for the first column plane, a configuration for scrambling column addresses of the first column plane to different column addresses of the first column plane. In some cases, the testing device may perform a fuse blow of a fuse associated with the first column plane to implement the determined configuration.

Abstract: Methods, systems, and devices for adjustable column address scramble using fuses are described. A testing device may detect a first error in a first column plane of a memory array and a second error in a second column plane of the memory array. The testing device may identify a first column address of the first column plane associated with the first error and a second column address of the second column plane based on detecting the first error and the second error. The testing device may determine, for the first column plane, a configuration for scrambling column addresses of the first column plane to different column addresses of the first column plane. In some cases, the testing device may perform a fuse blow of a fuse associated with the first column plane to implement the determined configuration.

Abstract: Methods, systems, and devices for adjustable column address scramble using fuses are described. A testing device may detect a first error in a first column plane of a memory array and a second error in a second column plane of the memory array. The testing device may identify a first column address of the first column plane associated with the first error and a second column address of the second column plane based on detecting the first error and the second error. The testing device may determine, for the first column plane, a configuration for scrambling column addresses of the first column plane to different column addresses of the first column plane. In some cases, the testing device may perform a fuse blow of a fuse associated with the first column plane to implement the determined configuration.

Abstract: A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as delay lock loops during row activations and read/write memory operations. A switch connects the array power bus to another separate power bus for a limited period of time during a DRAM refresh cycle to provide additional current to the DRAM arrays. The switch disconnects the array power bus from the other power bus preferably before the end of the refresh cycle.

Abstract: A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as delay lock loops during row activations and read/write memory operations. A switch connects the array power bus to another separate power bus for a limited period of time during a DRAM refresh cycle to provide additional current to the DRAM arrays. The switch disconnects the array power bus from the other power bus preferably before the end of the refresh cycle.

Abstract: An apparatus and system for locating a person includes a G.P.S. cellular watch removably secured to the person, which acts as a mobile transmitter. When panic buttons on the watch are depressed simultaneously, a location signal is emitted by the watch so that a remote Emergency Control Center (ECC) is informed of the person's location, the panic buttons also automatically starting a photo/video recorder, images from which can be viewed in the ECC, as well as an audio microphone, which allows the ECC to listen, record and save all sounds received by the microphone. The watch face also comprises a security code pad, with a corresponding key pad entry also unique to that apparatus, to lock or unlock the band from the user's wrist, without which entry the apparatus cannot be removed from the person.

Abstract: A method and circuitry for boosting a driven signal along a circuit line so as to reduce RC delays is disclosed. In one embodiment, the circuitry includes a line amplifier positioned at a distance from the circuitry that drives signals onto the line, for example, across a memory array. The line amplifier detects the driven signal on the line at early stages, and even before the signal reaches its full potential, the amplifier amplifies that signal and drives it back to the line to help boost the detected signal. In a preferred embodiment, the amplifier comprises a differential amplifier capable of boosting one of two input signal lines. In an alternative embodiment, the amplifier output may additionally input to a feedback loop, which loop ultimately drives a pull-up transistor to boost the detected signal and passes it back to the line to even further assist the differential amplifier in boosting.

Abstract: A data path for coupling data between a memory cell and an input/output (IO) line sense amplifier. An IO line coupling circuit is coupled to a pair of global data lines and a pair of local data lines to couple and decouple each of the global data lines to and from a voltage supply based on the voltage levels of the local data lines for the memory read operation. For the memory write operation, the IO line coupling circuit couples and decouples each of the global data lines to and from a respective one of the local data lines. The data path also includes a first precharge circuit coupled to the global data lines to couple the global data lines to ground to precharge the signal lines prior to a memory read or write operation, and can further include a test compression circuit coupled to the global data lines.

Abstract: A self-timed data ordering method and circuit for multi-data rate memories orders a plurality of data words substantially simultaneously retrieved during successive read operations of a memory device. A data word ordering designator is stored from each of the successive read operations and managed in a first-in first-out manner. The data word ordering designator configures ordering circuitry for the desired ordering of the plurality of data words simultaneously retrieved. Following the ordering of the plurality of data words, the properly ordered data words are latched in their desired order for subsequent delivery. Once the properly ordered data words are latched, the ordering circuitry is reconfigured according to the next oldest data word ordering designator. The data word ordering designator retains the pipelined ordering of the corresponding read operations to the corresponding memory banks of the memory device.

Abstract: The present invention includes a circuit, system and method for selectively turning off internal clock drivers to reduce operating current. The present invention may be used to reduce power consumption by reducing operating current in a memory device. Operating current may be reduced by turning off internal clock drivers that deliver a clock signal during selected periods of time. According to an embodiment of clock control circuitry of the present invention, an internal clock is disabled if a no operation command is detected during periods of time when no read or write burst operation is taking place. Methods, memory devices and computer systems including the clock control circuitry and its functionality are also disclosed.

Abstract: A data path for coupling data between a memory cell and an input/output (IO) line sense amplifier. An IO line coupling circuit is coupled to a pair of global data lines and a pair of local data lines to couple and decouple each of the global data lines to and from a voltage supply based on the voltage levels of the local data lines for the memory read operation. For the memory write operation, the IO line coupling circuit couples and decouples each of the global data lines to and from a respective one of the local data lines. The data path also includes a first precharge circuit coupled to the global data lines to couple the global data lines to ground to precharge the signal lines prior to a memory read or write operation, and can further include a test compression circuit coupled to the global data lines.

Abstract: A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as delay lock loops during row activations and read/write memory operations. A switch connects the array power bus to another separate power bus for a limited period of time during a DRAM refresh cycle to provide additional current to the DRAM arrays. The switch disconnects the array power bus from the other power bus preferably before the end of the refresh cycle.

Abstract: A data path for coupling data between a memory cell and an input/output (IO) line sense amplifier. An IO line coupling circuit is coupled to a pair of global data lines and a pair of local data lines to couple and decouple each of the global data lines to and from a voltage supply based on the voltage levels of the local data lines for the memory read operation. For the memory write operation, the IO line coupling circuit couples and decouples each of the global data lines to and from a respective one of the local data lines. The data path also includes a first precharge circuit coupled to the global data lines to couple the global data lines to ground to precharge the signal lines prior to a memory read or write operation, and can further include a test compression circuit coupled to the global data lines.

Abstract: A data path for coupling data between a memory cell and an input/output (IO) line sense amplifier. An IO line coupling circuit is coupled to a pair of global data lines and a pair of local data lines to couple and decouple each of the global data lines to and from a voltage supply based on the voltage levels of the local data lines for the memory read operation. For the memory write operation, the IO line coupling circuit couples and decouples each of the global data lines to and from a respective one of the local data lines. The data path also includes a first precharge circuit coupled to the global data lines to couple the global data lines to ground to precharge the signal lines prior to a memory read or write operation, and can further include a test compression circuit coupled to the global data lines.

Abstract: A self-timed data ordering method and circuit for multi-data rate memories orders a plurality of data words substantially simultaneously retrieved during successive read operations of a memory device. A data word ordering designator is stored from each of the successive read operations and managed in a first-in first-out manner. The data word ordering designator configures ordering circuitry for the desired ordering of the plurality of data words simultaneously retrieved. Following the ordering of the plurality of data words, the properly ordered data words are latched in their desired order for subsequent delivery. Once the properly ordered data words are latched, the ordering circuitry is reconfigured according to the next oldest data word ordering designator. The data word ordering designator retains the pipelined ordering of the corresponding read operations to the corresponding memory banks of the memory device.

Abstract: A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as delay lock loops during row activations and read/write memory operations. A switch connects the array power bus to another separate power bus for a limited period of time during a DRAM refresh cycle to provide additional current to the DRAM arrays. The switch disconnects the array power bus from the other power bus preferably before the end of the refresh cycle.