Abstract: An information file is inspected for an identity of a locking service associated with a desired file. The locking service is contacted, and the locking service grants access if the desired file is available.

Abstract: One embodiment is a method for enabling a first circuit analysis tool to flatten a hierarchical design for processing by a second circuit analysis tool. The method comprises reading a logical representation of the hierarchical design; and, for each block of the hierarchical design, loading RC information for the block from an RC model of the hierarchical design and writing a flat representation of each instantiation of the block to the second circuit analysis tool.

Abstract: A method for use by a circuit analysis tool for selectively applying configuration information from multiple sources to configuration data elements (“CDEs”) stored in a database is described. The method comprises comparing a data source indicator (“DSI”) of a configuration command with a DSI of a corresponding CDE; if the DSI of the configuration command takes precedence over the DSI of the corresponding CDE, applying the configuration command thereto; and if the DSI of the configuration command does not take precedence over the DSI of the corresponding CDE, disregarding the configuration command.

Abstract: A method for optimizing relationships between logic commands defining a circuit design is described. The method comprises, for each logic command determining whether the logic command is a primitive logic command; and, responsive to the logic command not being a primitive logic command, decomposing the logic command into its most primitive form.

Abstract: A method of using a software tool to analyze a VLSI circuit is described. In one embodiment, the method comprises, prior to initiating analysis of the circuit, performing a complexity check on the circuit; responsive to the circuit failing the complexity check, aborting analysis of the circuit; and responsive to the circuit passing the complexity check, initiating analysis of the circuit and continuing analysis of the circuit until expiration of a predetermined time period following the initiating.

Abstract: A method for controlling analysis by an analysis tool of multiple instantiations of a circuit in a hierarchical circuit design is described. The method comprises providing a user-selected analysis option to the analysis tool; analyzing a first instantiation of the circuit as specified by the analysis option; and responsive to the first instantiation of the circuit passing the analysis, terminating analysis of the circuit.

Abstract: A method for optimizing relationships between logic commands defining a circuit design input to an analysis tool is described. The method comprises, responsive to a determination that a value of logic level of a signal can be inferred and responsive to an attempt by the analysis tool to set the logic level of the signal to a calculated value, determining whether the calculated value is equal to the inferred value; and if the calculated value is equal to the inferred value, setting the logic level of the signal to the inferred value.

Abstract: A method and system for determining connectivity of a hierarchical circuit design. Hierarchical interface connections in the circuit design are evaluated by determining, for each block instance in each of the hierarchical blocks in the design, whether each port instance, on each block instance, is connected a net in a parent block; and whether each port, in each of the hierarchical blocks, is connected to a net within the block. A warning message is generated upon detection of at least one disconnected net within the hierarchical blocks.

Abstract: Systems, methods and software products determine activity factors of a circuit design. An activity factor is assigned to one or more node types. One or more signal nets from a netlist of the circuit design are read. The signal nets are processed to associate one of the node types with each of the signal nets. An activity factor is determined for each of the signal nets based upon node type.

Abstract: A system and method for determining unmatched design elements in a circuit. The system determines instances of a first type and a second type of the design elements that are connected to a specific node in the circuit, and stores the gate signal name for each determined said occurrence of the first type of design element in a first list. The gate signal name for each determined said occurrence of the second type of design element is than stored in a second list. A value of a design element characteristic and indicia thereof for each determined said occurrence of the first and the second types of the design elements is than stored.

Abstract: Methods, systems, software products perform circuit analysis on a circuit design. Instantiation paths for one or more design blocks of the circuit design are determined. Select information is recursively accumulated for each of the design blocks. Instantiation characteristics are applied to the accumulated information for each instance of the design blocks based upon instantiation hierarchy of the instance within the circuit design.

Abstract: Systems, methods, and software products iteratively traverse a hierarchical circuit design. An initial net and an instance history that uniquely defines the initial net within the design are selected. The initial net and the instance history are appended to a list of nets to be processed. The initial net and the instance history are inserted into a set of visited nets. Each additional net connected to the initial net is visited in response to a first request from a user. The initial net and each additional net are returned in response to a second request from the user.

Abstract: Methods, systems and software products are described for determining applicable configuration information for use in analysis of a computer aided design. A state machine is generated using information contained in a plurality of configuration commands. A design element name, associated with a design element, is applied to the state machine. The state machine generates a list including configuration information applicable to the design element.

Abstract: System and method for analyzing design elements in a CAD tool design. A configuration element generator encodes information in a configuration command to generate a configuration element associated with at least one of the design elements. A sequencer, coupled to the configuration element generator, tags the configuration element with a sequence number. A computer memory, coupled to the sequencer, stores the configuration element. A processor, coupled to the computer memory, applies, to the design element that is of interest, each stored said configuration element associated with the design element of interest, in an order indicated by the sequence number. A configuration element is an encoding of data comprising formatted information associated with a design.

Abstract: Systems, methods, software products identify a data source used in analysis of a circuit design. Data source information, including identification of the data source used to generate data for an entity in a design portion of interest in the circuit design, is retrieved. The data source information is formatted as a bit vector associated with the entity, wherein each of a plurality of bits in the bit vector comprises indicia applicable to the entity. The bit vector is processed to generate formatted output.

Abstract: A method and system for determining wire capacitance for a VLSI circuit design, comprising determining all hierarchical blocks of a portion of the design; storing, for a plurality of the blocks, indicia of the most accurate one of a plurality of wire capacitance data sources; generating a wire capacitance database with an entry for each net in at least a plurality of the blocks, using information stored in at least one of the wire capacitance data sources; generating a hierarchical connectivity model for the design; and using the hierarchical connectivity model and said wire capacitance database to determine a cumulative wire capacitance value for each HLSN in each of the blocks in a portion of the design to be analyzed.

Abstract: Systems, methods, and software products determine a highest level signal name in a hierarchical circuit design. A signal path is traced into a hierarchically lower level of the circuit design from a predetermined net in the circuit design to a predetermined terminal instance, while adding indicia, to an instance history list, of each subsequent instance encountered. A port instance is determined on the terminal instance associated with a selected net for which the highest level signal name is to be determined. The selected net is designated as the current net. For each stored indicia in the instance history list, the net connected to the current net in a hierarchical parent of the instance identified by the indicia is determined, to establish a next current net. If a condition exists wherein there is no connection from the current net to a hierarchically higher level instance, then the current net is established as the highest level signal name for the selected net.

Abstract: Systems, methods, software products utilize fast analysis information during detailed analysis of a circuit design. One or more design blocks of the circuit design are electronically analyzed to determine fast analysis results based upon assumptions of ported signal nets of each one of the design blocks. Next, it is determined whether hierarchical signal net connectivity of block instances of the design blocks and the assumptions match. If the hierarchical signal net connectivity matches the assumptions, the fast analysis results are utilized to generate detailed analysis results. If the hierarchical signal net connectivity does not match the assumptions, the one or more blocks in the hierarchical signal net connection are electronically analyzed to generate detailed analysis results.

Abstract: Methods, systems, software products analyze a circuit design with reduced memory utilization. Access to at least one block of the circuit design is detected. If the one block is not loaded within a circuit model of computer memory, a determination is made whether loading the one block into the circuit model would exceed a predefined maximum utilization of the computer memory. If loading the one block into the circuit model would exceed the predefined maximum utilization, one or more blocks from the circuit model are unloaded and the one block is loaded into the circuit model. If loading the one block into the circuit model would not exceed the predefined maximum utilization, the one block is loaded into the circuit model.

Abstract: A method and system for establishing consistency, with respect to a data model, between sub-modules within an E-CAD tool. A consistency database, including at least one consistency indicator for each block of interest in the data model, is initially created. One or more of the sub-modules is then executed to perform an analysis of a current version of the data model. At least one data field value, corresponding to the consistency indicator, is compared for each block of interest, in source files in the current version of the data model being analyzed, against a corresponding consistency indicator in the consistency database. A warning is issued, indicating a possible discrepancy between data in the current version of the data model and corresponding data in a previous version of the data model, if a difference is detected between at least one data field value in the current version of the data model being analyzed and the corresponding consistency indicator.