Abstract: A phase locked local oscillator loop of a frequency synthesizer tuning system for a television receiver includes a programmable frequency divider for deriving an output signal having a period which is N times the period of its input signal, N being the number in MHz of the local oscillator frequency required for tuning the receiver to a selected channel (e.g., N = 101 for U.S. channel 2). The "divide by" number N is controlled by first counting the input signal pulses in groups of (S) pulses, where (S) is a factor equal to the channel separation in MHz (6 in the U.S.). Counting by groups of S continues until the number of such groups equals the channel number, e.g., 2 for channel 2, 83 for channel 83, and then continues for an additional predetermined number of groups of S dependent on the band in which the selected channel resides.

Abstract: A CMOS shift register cell comprising four transistors and two capacitance elements. Data is temporarily stored in the cell by precharging one capacitance through one of the transistors and then discharging it or not through another of the transistors depending on the input signal level. The second capacitance may be precharged through the third transistor and then discharged or not through the fourth transistor, depending upon the value of the temporarily stored charge.