Patents by Inventor George Romas

George Romas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10339499
    Abstract: To propagate compliance and governance (C&G) policies, a parser including natural language processing is used to deconstruct a set of organization C&G policies from a set of C&G documents to identify and record a parsed set of categorized C&G policies. A configuration parameter analyzer deconstructs and parses a plurality of C&G configuration parameters of an application program to identify and record a set of application C&G configuration parameters each comprising a purpose and a unit of measure. A reconciliation arranger receives the set of categorized C&G policies and the set of application C&G configuration parameters and maps the categorized C&G policies for the correct purpose and the unit of measure to the respective application C&G configuration parameters. The reconciliation arranger propagates and secures the application program with the respective set of mapped application C&G configuration parameters from mapped C&G policies.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: July 2, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Robert Rathbun, Jeff Kalibjian, George Romas
  • Publication number: 20170293887
    Abstract: To propagate compliance and governance (C&G) policies, a parser including natural language processing is used to deconstruct a set of organization C&G policies from a set of C&G documents to identify and record a parsed set of categorized C&G policies. A configuration parameter analyzer deconstructs and parses a plurality of C&G configuration parameters of an application program to identify and record a set of application C&G configuration parameters each comprising a purpose and a unit of measure. A reconciliation arranger receives the set of categorized C&G policies and the set of application C&G configuration parameters and maps the categorized C&G policies for the correct purpose and the unit of measure to the respective application C&G configuration parameters. The reconciliation arranger propagates and secures the application program with the respective set of mapped application C&G configuration parameters from mapped C&G policies.
    Type: Application
    Filed: April 29, 2015
    Publication date: October 12, 2017
    Inventors: Robert RATHBUN, Jeff KALIBJIAN, George ROMAS
  • Patent number: 9391055
    Abstract: Power modules with reduced parasitic inductances are provided. A power module includes a first substrate including a first electrically-conductive layer and a second substrate including a second electrically-conductive layer. These substrates may be stacked on each other. A scalable network of power switches may be arranged on the substrates. Power bars may be connectable to the electrically-conductive layers through electromechanical interfaces at selectable interface locations. The locations and/or type of interface may be selectable based on the arrangement of the switches. The first and second electrically-conductive layers may be disposed on mutually opposed surfaces of a dielectric layer having a thickness chosen to effect a level of coupling between respective source and return current paths provided by the electrically-conductive layers.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: July 12, 2016
    Assignee: LOCKHEED MARTIN CORPORATION
    Inventors: Gregory George Romas, Jr., David L. Hoelscher, Thomas Eugene Byrd
  • Patent number: 9385620
    Abstract: A multiport AC link converter includes a resonant AC link, an input port, an output port, and a plurality of switches. A first subset of the switches is between the input port the resonant link and a second subset of the switches is between the resonant link and the output port. The switch sequencing for the input port is selected and executed independently of the switch sequencing for the output port the switch sequencings for the output port is selected and executed independently of that for the input port.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: July 5, 2016
    Assignee: Lockheed Martin Corporation
    Inventors: David Louis Hoelscher, Em Hoang, Gregory George Romas, Jr., Brad Clinton Ortloff, Jatin Nikul Mehta, Daniel Homiak
  • Publication number: 20140152373
    Abstract: Power modules with reduced parasitic inductances are provided. A power module includes a first substrate including a first electrically-conductive layer and a second substrate including a second electrically-conductive layer. These substrates may be stacked on each other. A scalable network of power switches may be arranged on the substrates. Power bars may be connectable to the electrically-conductive layers through electromechanical interfaces at selectable interface locations. The locations and/or type of interface may be selectable based on the arrangement of the switches. The first and second electrically-conductive layers may be disposed on mutually opposed surfaces of a dielectric layer having a thickness chosen to effect a level of coupling between respective source and return current paths provided by the electrically-conductive layers.
    Type: Application
    Filed: December 3, 2013
    Publication date: June 5, 2014
    Applicant: LOCKHEED MARTIN CORPORATION
    Inventors: Gregory George Romas, JR., David L. Hoelscher, Thomas Eugene Byrd
  • Patent number: 8130481
    Abstract: Electrostatic discharge (ESD) protection circuits for self-protecting cascode stages are disclosed. In one example, an ESD protection circuit is described. A cascode stage is configured to selectively couple an output pad to a reference terminal. An ESD sensor may detect a change in voltage indicative of an ESD event occurring at the output pad, causing a gate drive to turn on the cascode stage to conduct ESD current in response to detection of the ESD event at the output pad. A leakage blocker is also included to prevent leakage current from the cascode stage to the gate drive while there is not an ESD event.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: March 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Jinyu Yang, Dening Wang, Gregory George Romas, Jr.
  • Publication number: 20090040678
    Abstract: Electrostatic discharge (ESD) protection circuits for self-protecting cascode stages are disclosed. In one example, an ESD protection circuit is described. A cascode stage is configured to selectively couple an output pad to a reference terminal. An ESD sensor may detect a change in voltage indicative of an ESD event occurring at the output pad, causing a gate drive to turn on the cascode stage to conduct ESD current in response to detection of the ESD event at the output pad. A leakage blocker is also included to prevent leakage current from the cascode stage to the gate drive while there is not an ESD event.
    Type: Application
    Filed: August 5, 2008
    Publication date: February 12, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jinyu Yang, Dening Wang, Gregory George Romas, JR.
  • Patent number: 5709280
    Abstract: A sealed lead-acid tray assembly for a motive-powered vehicle such as, for example, a Class 1-3 truck, comprises a bottom tray with a base, side and back walls defining a lower and an upper cell-receiving space and a first set of short sealed lead-acid cells, typically having a height of no more than about 14 inches, vertically positioned in the lower cell-receiving space, a top tray support structure positioned in the bottom tray, and a top tray located on the top tray support and having a second set of short sealed lead-acid cells in the top tray which is located in the upper cell-receiving space of the bottom tray, the respective cells being suitably electrically connected together.
    Type: Grant
    Filed: October 13, 1995
    Date of Patent: January 20, 1998
    Assignee: GNB Technologies, Inc.
    Inventors: Gordon C. Beckley, Kwok K. Chan, George Romas
  • Patent number: D356022
    Type: Grant
    Filed: April 27, 1993
    Date of Patent: March 7, 1995
    Inventors: Jeffrey T. Kostos, George Romas