Abstract: A fixed terrestrial user terminal antenna for use with a satellite communication systems in which satellites orbit earth in a constellation comprised of a plurality of spaced orbital planes with each orbital plane of the plurality of orbital planes having a plurality of satellites. The user terminal antenna comprising a base with a tilt plate connected to the base. The tilt plate having a one-dimensional electronically scanned phased array antenna that scans along a single axis is attached to the tilt plate so that the array antenna tilts with the tilting of the tilt plate. The array antenna tracks individual satellites of the plurality of satellites in an orbital plane of the plurality of orbital planes as the individual satellites travel through a field of view of the array antenna.

Abstract: A configurable circuit includes a first subcircuit (206) and a second subcircuit (410) each having a static power dissipation. A first bias circuit (402), coupled to the first subcircuit (206), provides a first bias level to the first subcircuit (206). Similarly, a second bias circuit (412), coupled to the second subcircuit (410), provides a second bias level to the second subcircuit (410). A logic circuit (403) is coupled to the first bias circuit (402) and the second bias circuit (412) and selectively provides a first signal to the first bias circuit (402). In response to the first signal, the first bias circuit (402) changes the bias level provided to the first subcircuit (206). The changed bias level disables the first subcircuit (206), substantially reducing the static power dissipation of the first subcircuit (206) while allowing the second subcircuit (410) to continue operating. In one embodiment, the circuit is a crosspoint switch with multiplexer subcircuits.

Abstract: A high speed packet switch which is inherently non-blocking, requires a minimum amount of buffering, is modular and degrades gracefully with failures. The output destination buffers can each absorb data at the full switch rate to avoid contention and they are filled evenly to minimize buffer size. The architecture only requires few parts types (multiplexers, demultiplexers and crosspoint switches) to operate at high speeds. The output list offers considerable flexibility in the way the data is output, whether it is by priority and/or by time division multiplexed sub destinations.

Abstract: A system for performing a self test on a circuit without interrupting its normal function. Several embodiments of a self-test system (10, 60, 80, 100, 120) are disclosed, each of which include a test generator (22) that generates a test signal selectively applied to a circuit under test (CUT) (12, 122). The CUT produces an output signal that is analyzed to determine whether the circuit is operating properly. In several of the embodiments, a signature analyzer (44) compares the signature of the output signal to a predetermined expected signature after a sequence of test vectors have been performed on the CUT. In a fault-tolerant embodiment of the self-test system (100), a plurality of CUTs are evaluated in respect to the output signal produced thereby, both when operating to process a normal input signal and, when processing a test signal.

Abstract: An FFL/QFL family of logic gates is disclosed, preferably implemented with GaAs MESFET devices and providing enhanced speed-power characteristics. Although a number of gate configurations are disclosed, a NOR gate 26 constructed in accordance with this invention includes a pair of normally OFF input transistors Q1 and Q7, which receive inputs A and B. Current sources Q2 and Q3 couple the transistors to the supply voltage V.sub.DD and ground, respectively. A control transistor Q6 is also coupled to the input and source transistors. An output section 30 responds to the combined operation of transistors Q1, Q2, Q3, Q6, and Q7 to produce an output C in accordance with conventional NOR logic. More particularly, upon application of a high logic input A or B to transistors Q1 and/or Q7, transistors Q1 and/or Q7 and Q6 turn ON and the output C is at a logic low level. If both inputs A and B are low, however, transistors Q1, Q6, and Q7 remain OFF, and the output C is at a high logic level.

Abstract: A high performance logic family for GaAs Enhancement/Depletion mode MESFETs is disclosed. The inventive logic family exhibits a large noise margin with little sacrifice in speed/power performance.

Abstract: An integrated logic circuit comprises a direct coupled FET logic input stage and a super buffer logic output stage. The input stage comprises a depletion-mode FET having its drain connected to a first reference potential level and having its gate and source connected together, and a first enhancement mode FET structure having its drain connected to the source of the depletion-mode FET, its source connected to a second, lower reference potential level and having at least one gate connected to receive an input logical signal. The super buffer logic output stage comprises a second enhancement mode FET structure that is essentially identical to the first enhancement mode FET structure, the source of the second enhancement mode FET structure being connected to the second reference potential level and the gate of the second enhancement mode FET structure being connected to the gate of the first enhancement mode FET structure.

Abstract: An integrated circuit package comprises at least two integrated circuit chips each having a plurality of contact pads arranged in a first pattern on the interconnect face of the chip, and an elastic sheet-form interconnect member. The interconnect member has at least two main face areas, associated with the chips respectively, and comprises dielectric material and conductor runs supported by the dielectric material in mutually electrically insulated relationship and having termination points arranged in at least two second patterns at the main face areas respectively and corresponding with the first patterns respectively. The interconnect face of each is in confronting relationship with the associated main face area of the interconnect member, and the contact pads of the chip and the termination points of the associated main face area are in mutually registering relationship. A metallurgical bond is formed between each contact pad and the corresponding termination point.