Abstract: This invention provides the structure for a two-phase charge coupled storage device. Alternate regions of thicker and thinner silicon dioxide are grown upon a silicon substrate. These silicon dioxide regions are covered with a layer of deposited, undoped polysilicon. A layer of silicon dioxide is grown over the polysilicon. Ion implantation is applied to cause isolated regions of conductivity in the polysilicon. Then contact windows are cut in the upper most layer of silicon dioxide exposing the polysilicon therethrough and a metal coating is deposited in the contact windows. Two-phase signals are applied to the resulting electrodes to advance charges at the surface of the silicon substrate.

Abstract: A process is described for forming a plurality of polysilicon runs on the surface of a semiconductor substrate, such as a silicon substrate, at least one of the polysilicon runs having a resistor portion formed therein, and at least one of the polysilicon runs forming the conductive gate electrode of a self-aligned insulated silicon gate field effect device.

Abstract: A charge coupled device (CCD) register includes a first group of CCD cells coupled horizontally together. Each of the CCD cells includes a "first phase location" and a "second phase location". The register includes a plurality of CCD loops, each of the CCD loops beginning at the first phase location of a respective one of the CCD cells and ending at the second phase location of the same CCD cell. Each of the CCD loops includes the same number of sequentially coupled CCD cells. The CCD register has a very high density of CCD cells, and requires far fewer regeneration devices than a serial CCD register with the same number of CCD cells.

Abstract: A sense line termination circuit is provided intercoupled between a sense line of a plurality of static memory cells and a supply bus of high pull-up voltage to provide fast access to the memory cells with limited medium power dissipation. The termination circuit functions to pull up the sense line toward a predetermined intermediate high voltage value (which is about one threshold voltage Vt below the high pull-up voltage) when no memory cell has a low voltage memory node coupled to the sense line. The sense line termination circuit limits the voltage excursion of the sense lines and also permits the sense line to be pulled down with predetermined current limitation to a low voltage value when the sense line is coupled to a low voltage memory node.

Abstract: An improved driving circuit is provided especially for use in an integrated circuit semiconductor memory which operates on low power supply voltage, such as 5 volts, the drive circuit employing field effect transistors coupled with bootstrap capacitor devices and responsive to an input pulse for supplying, at its output terminal, a pulse having a peak voltage potential substantially equal to the power supply voltage value despite the inherent threshold voltage drops of the field effect transistors utilized. In the drive circuit, in response to an input pulse, the reference voltage for charged capacitor devices is switched between a first level and a raised second, higher level to place the capacitor devices in series with each other and the raised reference voltage to overdrive an output switch device so as to connect substantially its full power supply voltage to its output terminal during a corresponding output pulse.

Abstract: This invention provides the structure for a two-phase charge coupled storage device. Alternate regions of thicker and thinner silicon dioxide are grown upon a silicon substrate. These silicon dioxide regions are covered with a layer of deposited, undoped polysilicon. A layer of silicon dioxide is grown over the polysilicon. Ion implantation is applied to cause isolated regions of conductivity in the polysilicon. Then contact windows are cut in the upper most layer of silicon dioxide exposing the polysilicon therethrough and a metal coating is deposited in the contact windows. Two-phase signals are applied to the resulting electrodes to advance charges at the surface of the silicon substrate.

Abstract: A clamped push-pull driver circuit suitable for driving high capacitive loads includes a bootstrap MOS inverter circuit driving an MOS push-pull driver circuit. A regulator circuit including a plurality of diode-connected MOSFETs is coupled between the output of the MOS bootstrap inverter and a ground conductor. A MOSFET (the feedback device) having its gate electrode coupled to the output of the MOS push-pull circuit is connected in series with the diode-connected MOSFETs. Rapid rise time and short delay are achieved at the output of the clamped push-pull driver circuit, since the regulator circuit does not begin to conduct current (i.e., does not start the clamping action) until the output voltage of the push-pull driver circuit has exceeded two thresholds. Thus a large drive capability is provided to initiate the rising action of the output signal and clamping only begins to occur after the output is already rising towards a higher virtual final level than that which clamping will allow.

Abstract: The number of devices and integrated circuit area required to enter new data or to recirculate data in a charge coupled storage memory is reduced by employing separated charge source areas interconnected to selective enabling means and appropriate phasing signals.