Abstract: A method and system for locating a dependent by a guardian entity at a locality using RFID technology is disclosed. A RFID tag is situated with the dependent and a plurality of RFID reader devices capable of communicating with the RFID tag are distributed about the locality. A processor is directing communications between the RFID tag and the plurality of RFID reader devices, and is tracking the RFID tag. An authenticating system, which uniquely associates the RFID tag with the guardian entity, validates commands pertaining to the tracking of the RFID tag. The processor upon receiving a validated command generates a response, which includes location information regarding the dependent.

Abstract: A method and system for locating a dependent by a guardian entity at a locality using RFID technology is disclosed. A RFID tag is situated with the dependent and a plurality of RFID reader devices capable of communicating with the RFID tag are distributed about the locality. A processor is directing communications between the RFID tag and the plurality of RFID reader devices, and is tracking the RFID tag. An authenticating system, which uniquely associates the RFID tag with the guardian entity, validates commands pertaining to the tracking of the RFID tag. The processor upon receiving a validated command generates a response, which includes location information regarding the dependent.

Abstract: A method and system for locating a dependent by a guardian entity at a locality using RFID technology is disclosed. A RFID tag is situated with the dependent and a plurality of RFID reader devices capable of communicating with the RFID tag are distributed about the locality. A processor is directing communications between the RFID tag and the plurality of RFID reader devices, and is tracking the RFID tag. An authenticating system, which uniquely associates the RFID tag with the guardian entity, validates commands pertaining to the tracking of the RFID tag. The processor upon receiving a validated command generates a response, which includes location information regarding the dependent.

Abstract: A method and system for locating a dependent by a guardian entity at a locality using RFID technology is disclosed. A RFID tag is situated with the dependent and a plurality of RFID reader devices capable of communicating with the RFID tag are distributed about the locality. A processor is directing communications between the RFID tag and the plurality of RFID reader devices, and is tracking the RFID tag. An authenticating system, which uniquely associates the RFID tag with the guardian entity, validates commands pertaining to the tracking of the RFID tag. The processor upon receiving a validated command generates a response, which includes location information regarding the dependent.

Abstract: A method and system for locating a dependent by a guardian entity at a locality using RFID technology is disclosed. A RFID tag is situated with the dependent and a plurality of RFID reader devices capable of communicating with the RFID tag are distributed about the locality. A processor is directing communications between the RFID tag and the plurality of RFID reader devices, and is tracking the RFID tag. An authenticating system, which uniquely associates the RFID tag with the guardian entity, validates commands pertaining to the tracking of the RFID tag. The processor upon receiving a validated command generates a response, which includes location information regarding the dependent.

Abstract: A method and system for locating a dependent by a guardian entity at a locality using RFID technology is disclosed. A RFID tag is situated with the dependent and a plurality of RFID reader devices capable of communicating with the RFID tag are distributed about the locality. A processor is directing communications between the RFID tag and the plurality of RFID reader devices, and is tracking the RFID tag. An authenticating system, which uniquely associates the RFID tag with the guardian entity, validates commands pertaining to the tracking of the RFID tag. The processor upon receiving a validated command generates a response, which includes location information regarding the dependent.

Abstract: A method and system for locating a dependent by a guardian entity at a locality using RFID technology is disclosed. A RFID tag is situated with the dependent and a plurality of RFID reader devices capable of communicating with the RFID tag are distributed about the locality. A processor is directing communications between the RFID tag and the plurality of RFID reader devices, and is tracking the RFID tag. An authenticating system, which uniquely associates the RFID tag with the guardian entity, validates commands pertaining to the tracking of the RFID tag. The processor upon receiving a validated command generates a response, which includes location information regarding the dependent.

Abstract: A method and system for locating a dependent by a guardian entity at a locality using RFID technology is disclosed. A RFID tag is situated with the dependent and a plurality of RFID reader devices capable of communicating with the RFID tag are distributed about the locality. A processor is directing communications between the RFID tag and the plurality of RFID reader devices, and is tracking the RFID tag. An authenticating system, which uniquely associates the RFID tag with the guardian entity, validates commands pertaining to the tracking of the RFID tag. The processor upon receiving a validated command generates a response, which includes location information regarding the dependent.

Abstract: A storage latch comprising a gate insulating layer over the substrate, shallow trenches formed through the insulating layer and in the substrate to provide device insulation; and doped regions in the substrate between the shallow trenches. The doped regions define sources and drains. Gate stacks are formed over regions of oxide adjacent the doped regions. A planarized insulator is formed between the gate stacks. Openings are provided in the planarized insulator for contacts to the doped regions and the gate stacks. Conductive material fills the openings to form contacts for the doped regions and for the gate stacks. A patterned layer of conductive material on the planarized insulator connects selected ones of the contacts for wiring portions of the latch.

Abstract: A field effect transistor having operating characteristics based on the control and modulation of the punch through phenomenon. The channel region between the source and the drain regions is appropriately doped such that the source and drain depletion regions overlap when no potential is applied between source and drain. The overlapped region in the absence of a gate field has a potential barrier. A gate voltage modulates the barrier to below the kT/q parameter. The source-to-drain fields also modulate the barrier.

Abstract: Shallow junctions of a first conductivity type in a semiconductor of the opposite conductivity type are fabricated by doping the substrate with a dopant of an opposite conductivity type than the first conductivity type to preamorphize portions of the substrate. The dopant of the opposite conductivity type must have a molecular weight that is higher than the molecular weight of the substrate. The substrate is then doped with the dopant of the first conductivity type to form the shallow junctions.

Abstract: A system for the detection of features in a semiconductor wafer for registration. An E-beam scans across an insulator covered with a metallic layer. The high energy electrons penetrate and cause the generation of electron/holes pairs. The drift or migration can be sensed as a current, the intensity of which is a function of the applied field strength. The field strength is in turn varied by the topology of the feature or the presence of a junction in the device. Since the E-beam position is known, registration occurs by correlation with the underlying feature as it is mapped out by sensing variations in current. The feature may be an alignment mark or a device under construction on the wafer.

Abstract: This interface permits the testing of high speed semiconductor devices (room-temperature chips) by a Josephson junction sampling device (cryogenic chip) without intolerable loss of resolution. The interface comprises a quartz pass-through plug which includes a planar transmission line interconnecting a first chip station, where the cryogenic chip is mounted, and a second chip station, where the semiconductor chip to be tested is temporarily mounted. The pass-through plug has a cemented long half-cylindrical portion and short half-cylindrical portion. The long portion carries the planar transmission line, the ends of which form the first and second chip mounting stations. The short portion completes the cylinder with the long portion for part of its length, where a seal can be achieved, but does not extend over the chip mounting stations. Sealing is by epoxy cement. The pass-through plug is sealed in place in a flange mounted to the chamber wall.

Abstract: A detector and/or mixer of electromagnetic energy in the microwave-infrared region of the electromagnetic spectrum comprised of a body of semiconductor material having a superlattice region consisting of, for example, InAs - GaSb wherein the thickness of alternating epitaxial planar layers is in the range of 30A to 80A. Incident radiation perpendicular to the planar regions results in an electric field being provided in the plane of the layers which causes a reduction in the superlattice bandwidth and accordingly an increase in the transverse effective mass of the carriers. This results in a decrease in the perpendicular conductivity through the superlattice region.

Abstract: A semiconductor inversion layer transistor which is compatible with semiconductor fabrication technology, and an integrated circuit which incorporates a plurality of such transistors. In one embodiment of the transistor, a P type indium arsenide base and a P type gallium antimonide emitter are used while the collector can be made of either P type gallium antimonide or N type indium arsenide. By the nature of the band alignment at the interface, the indium arsenide base has its Fermi level pinned in the conduction ban at the base-emitter junction and an assymetrically conducting charge barrier which is formed at this junction is preferential to injection of carriers flowing from the emitter to the base rather than vice versa. When the base-emitter junction is forward biased the electrons at the junction are projected across the base with minimal hole injection from base to emitter, thus providing a high gain transistor having excellent high frequency characteristics.

Abstract: A superlattice structure is disclosed in which alternating layers of semiductor alloy materials provide a one dimensional spatial periodic variation in band edge energy. A first layer of the superlattice device is an alloy including a first Group III material and a first Group V material, preferably In As, while the second layer is an alloy including a second Group III material different from the first Group III material and a second Group V material different from the first Group V material, and preferably GaSb. In the superlattice structure the valence band of the second alloy is closer to the conduction band of the first alloy than it is to the valence band of the first alloy.

Abstract: A heterojunction structure made of two semiconductor layers is disclosed in hich light is applied to the structure and absorbed, and the emission of light from the structure is controlled by an electric field applied perpendicularly to the planes of the layers. It is further disclosed that the device can be employed as a selective light filter or modulator.

Abstract: An optical device is disclosed which includes first and second superlattice emiconductor regions. The first superlattice semiconductor region includes a plurality of alternating barrier and light absorbing layers which absorbs light of a first light frequency. The second superlattice region also includes a plurality of alternating barrier and light absorbing layers. However, the light absorbing layers of the second superlattice semiconductor region absorbs light of a different frequency.