Patents by Inventor George Shchupak
George Shchupak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973032Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.Type: GrantFiled: March 8, 2023Date of Patent: April 30, 2024Assignee: Intel CorporationInventors: Smita Shridharan, Zheng Guo, Eric A. Karl, George Shchupak, Tali Kosinovsky
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Patent number: 11790978Abstract: An embodiment of a novel memory circuit is described that improves post aging performance of a shared VCC node with a write pre-charge on the supply line. A write pre-charge PMOS device is added to the shared VCC node in some embodiments. The write pre-charge circuit helps insure that the shared VCC node has a healthy voltage value at the beginning of a write phase and also enables the memory circuit to recover the shared VCC value after the write phase (e.g., immediately following), enabling a read operation after a write operation for a same register file entry or adjacent entries (e.g., entries connected to the same shared VCC node). Other embodiments are disclosed and claimed.Type: GrantFiled: September 23, 2019Date of Patent: October 17, 2023Assignee: Intel CorporationInventors: Bassel Daher, Ari-Shaul Leibman, George Shchupak, Or O Rotem
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Publication number: 20230223339Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.Type: ApplicationFiled: March 8, 2023Publication date: July 13, 2023Inventors: Smita SHRIDHARAN, Zheng GUO, Eric A. KARL, George SHCHUPAK, Tali KOSINOVSKY
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Patent number: 11640939Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.Type: GrantFiled: November 11, 2021Date of Patent: May 2, 2023Assignee: Intel CorporationInventors: Smita Shridharan, Zheng Guo, Eric A. Karl, George Shchupak, Tali Kosinovsky
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Patent number: 11513893Abstract: A system includes a compute circuit that preemptively performs a computation on a data word before receiving an indication of data errors from an error checking and correction (ECC) circuit. The ECC circuit reads the data word from a memory array and performs error detection and error correction on the data word. The compute circuit reads the data word and performs the computation on the data word to generate an output value, without waiting for the ECC circuit to check and correct the data word. In response to error detection in the data word by the ECC circuit, the compute circuit delays outputting the output value until correction of the output value in accordance with the error detection by the ECC circuit.Type: GrantFiled: December 21, 2020Date of Patent: November 29, 2022Assignee: Intel CorporationInventors: Somnath Paul, Charles Augustine, Chen Koren, George Shchupak, Muhammad M. Khellah
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Publication number: 20220077055Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.Type: ApplicationFiled: November 11, 2021Publication date: March 10, 2022Inventors: Smita SHRIDHARAN, Zheng GUO, Eric A. KARL, George SHCHUPAK, Tali KOSINOVSKY
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Patent number: 11205616Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.Type: GrantFiled: June 20, 2017Date of Patent: December 21, 2021Assignee: Intel CorporationInventors: Smita Shridharan, Zheng Guo, Eric A. Karl, George Shchupak, Tali Kosinovsky
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Publication number: 20210109809Abstract: A system includes a compute circuit that preemptively performs a computation on a data word before receiving an indication of data errors from an error checking and correction (ECC) circuit. The ECC circuit reads the data word from a memory array and performs error detection and error correction on the data word. The compute circuit reads the data word and performs the computation on the data word to generate an output value, without waiting for the ECC circuit to check and correct the data word. In response to error detection in the data word by the ECC circuit, the compute circuit delays outputting the output value until correction of the output value in accordance with the error detection by the ECC circuit.Type: ApplicationFiled: December 21, 2020Publication date: April 15, 2021Inventors: Somnath Paul, Charles Augustine, Chen Koren, George Shchupak, Muhammad M. Khellah
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Publication number: 20210090635Abstract: An embodiment of a novel memory circuit is described that improves post aging performance of a shared VCC node with a write pre-charge on the supply line. A write pre-charge PMOS device is added to the shared VCC node in some embodiments. The write pre-charge circuit helps insure that the shared VCC node has a healthy voltage value at the beginning of a write phase and also enables the memory circuit to recover the shared VCC value after the write phase (e.g., immediately following), enabling a read operation after a write operation for a same register file entry or adjacent entries (e.g., entries connected to the same shared VCC node). Other embodiments are disclosed and claimed.Type: ApplicationFiled: September 23, 2019Publication date: March 25, 2021Applicant: Intel CorporationInventors: Bassel Daher, Ari Leibman, George Shchupak, Or O Rotem
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Publication number: 20200098682Abstract: Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.Type: ApplicationFiled: June 20, 2017Publication date: March 26, 2020Inventors: Smita SHRIDHARAN, Zheng GUO, Eric A. KARL, George SHCHUPAK, Tali KOSINOVSKY
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Patent number: 8824198Abstract: A register file employing a shared supply structure to improve the minimum supply voltage.Type: GrantFiled: May 30, 2013Date of Patent: September 2, 2014Assignee: Intel CorporationInventors: Vivek K. De, DiaaEidin S. Khalil, Muhammad M. Khellah, Moty Mehalel, George Shchupak
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Publication number: 20130279241Abstract: A register file employing a shared supply structure to improve the minimum supply voltage.Type: ApplicationFiled: May 30, 2013Publication date: October 24, 2013Inventors: Vivek K. DE, DiaaEldin S. KHALIL, Muhammad M. KHELLAH, Moty MEHALEL, George SHCHUPAK
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Patent number: 8462541Abstract: A register file employing a shared supply structure to improve the minimum supply voltage.Type: GrantFiled: January 10, 2012Date of Patent: June 11, 2013Assignee: Intel CorporationInventors: Vivek De, DiaaEldin S. Khalil, Muhammad Khellah, Moty Mehalel, George Shchupak
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Publication number: 20120106285Abstract: A register file employing a shared supply structure to improve the minimum supply voltage.Type: ApplicationFiled: January 10, 2012Publication date: May 3, 2012Inventors: Vivek De, DiaaEldin S. Khalil, Muhammad Khellah, Moty Mehalel, George Shchupak
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Patent number: 8111579Abstract: A register file employing a shared supply structure to improve the minimum supply voltage.Type: GrantFiled: November 10, 2008Date of Patent: February 7, 2012Assignee: Intel CorporationInventors: Vivek De, DiaaEldin S. Khalil, Muhammad Khellah, Moty Mehalel, George Shchupak
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Publication number: 20100118637Abstract: A register file employing a shared supply structure to improve the minimum supply voltage.Type: ApplicationFiled: November 10, 2008Publication date: May 13, 2010Inventors: Vivek De, DiaaElden S. Khalil, Muhammad Kellah, Moty Mehalel, George Shchupak