Abstract: A processor is provided with a decoder, a memory connected to the decoder and an execution stage connected to the decoder. The decoder receives each instruction. Each time the decoder receives an instruction, if the instruction contains a symbolic reference, the decoder determines whether or not the symbolic reference has been resolved into a numeric operand. If the symbolic reference has been resolved into a numeric operand, the memory retrieves, from a numeric reference table, a numeric operand to which the symbolic reference has been resolved. The execution stage then executes the instruction on the retrieved numeric operand in place of the symbolic reference. If the symbolic reference has not been resolved into a numeric operand, then the execution stage searches a data object, which relates each symbolic reference to a memory slot in which a corresponding numeric operand is stored, for a numeric reference relating the symbolic reference to a corresponding numeric operand.

Abstract: A reorder buffer for an out-of-order issue/execute superscalar microprocessor is composed of a destination register unit, four data units, and a destination tag unit. The destination register and tag units are each made up of content addressable memory shift registers, while the data units are made up of random access memory shift registers which contain partial word operands. When an instruction is decoded, the destination register and tag units generate read and write match signals, respectively, for the data registers. The data registers are associated with corresponding lookup circuits and read/write driver cells. A valid bit is derived from a result byte input, and is used to selectively enable the lookup circuits and read/write driver cells to access the partial word operands in the data registers. Thus, the valid bit, in combination with the read and write match signals, provides the inventive reorder buffer with the ability to independently execute partial word operands in parallel.