Abstract: The specification describes a circuit for transmitting a drive pulse from a source of pulses to a capacitive load, such as a word line or a bit line in a monolithic memory. A discharge path is provided for discharging the capacitive load, thereby preventing false selection of a word or bit line and improving the timing performance of the monolithic memory. The discharge path is shown in the form of a field effect transistor having a source to drain path from the output node to a second node dischargeable to ground potential and is gated by the source of pulses.

Abstract: Disclosed is a technique for testing electronic storage arrays including bistable storage cells fabricated in accordance with integrated semiconductor technology. Also described is the testing of load devices in a flip flop storage cell which is connected to a pair of bit lines that are inaccessible for the direct application of test signals. Testing is performed by altering the time duration of signals applied to the memory cells under test.

Abstract: Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's. The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross-coupled pair. The load devices are never fully turned off so that complete D.C. stability is achieved with a four device cell because no one cell in an array of memory cells ever goes into a data retention mode.

Abstract: Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's. The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross-coupled pair. D.C. stability is achieved by conditioning the load FET devices into partial conduction during the stand-by state of the memory cell.

Abstract: Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's. The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross coupled pair. D.C. stability is achieved by conditioning the load FET devices into partial conduction during the stand-by state of the memory cell.

Abstract: disclosed is an apparatus for generating and controlling a desired substrate potential level or a semiconductor chip. A pulse source, such as an oscillator, provides a pulse train which, in combination with a control signal from the substrate voltage detector, selectively discharges a capacitor in a voltage level converter for obtaining a desired level of substrate potential. A feedback path through the substrate regulates the conductivity of a reference transistor in the substrate voltage detector providing the required control signal.