Patents by Inventor George Stojakovic

George Stojakovic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050207064
    Abstract: A method of forming a magnetic switching device is provided. The method includes depositing a bilayer hardmask, which may comprise a first mask layer of titanium nitride with a second mask layer of tungsten formed thereon. A first lithography process is performed to pattern the second mask layer, and a second lithography process is performed to pattern the first mask layer. Thereafter, the magnetic tunnel junction stack may be patterned in accordance with the first mask layer. An etching process may be performed to further pattern the first mask layer in accordance with the second mask layer. An optional passivation layer may be formed over the first mask layer and the second mask layer.
    Type: Application
    Filed: March 2, 2005
    Publication date: September 22, 2005
    Inventors: Gregory Costrini, John Hummel, George Stojakovic, Kia-Seng Low
  • Publication number: 20050051820
    Abstract: A method of fabricating a magnetic tunnel junction (MTJ) device is provided. A patterned hard mask is oxidized to form a surface oxide thereon. An MTJ stack is etched in alignment with the patterned hard mask after the oxidizing of the patterned hard mask. Preferably, the MTJ stack etch recipe includes chlorine and oxygen. Etch selectivity between the hard mask and the MTJ stack is improved.
    Type: Application
    Filed: September 10, 2003
    Publication date: March 10, 2005
    Inventors: George Stojakovic, Rajiv Ranade, Ihar Kasko, Joachim Nuetzel, Keith Milkove, Russell Allen, Young Lee, Kim Lee
  • Publication number: 20050045937
    Abstract: An Iridium barrier layer is between a contact plug and a bottom electrode of a capacitor. Etching is performed to pattern the bottom electrode and barrier layer using a fluorine-based recipe resulting in the formation of a first fence clinging to the sidewalls. Next the remaining barrier layer is etched using a CO-based recipe. A second fence is formed clinging to and structurally supported by the first fence. At the same time, the CO-based recipe etches away a substantial portion of the first fence to remove the structural support provided to the second fence. The second fence is therefore lifted-off from the sidewalls leaving the sidewalls substantially free of clinging fences. The etched barrier layer has a sidewall transition. The sidewalls have a relatively low taper angle above the sidewall transition and a relatively steep taper angle below the sidewall transition.
    Type: Application
    Filed: September 3, 2003
    Publication date: March 3, 2005
    Applicants: Infineon Technologies AG, Kabushiki Kaisha Toshiba
    Inventors: Ulrich Egger, Haoren Zhuang, George Stojakovic, Kazuhiro Tomioka
  • Patent number: 6815364
    Abstract: Disclosed is a method of tungsten-based hard mask etching of a wafer, comprising providing a patterned tungsten-based hard mask atop a metal-based surface of said wafer, etching through said pattern with a plasma etch that is selective for said metal-based surface with respect to tungsten, and executing a flash etch selective for tungsten, said etch of at least a minimum duration effective in removing substantially all defects caused by tungsten particulate contaminating said wafer. In another aspect of the first embodiment, said tungsten-based hard mask comprises a material selected from tungsten or an alloy thereof. In another aspect of the first embodiment, said metal based surface comprises a material selected from aluminum or an alloy thereof.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: November 9, 2004
    Assignee: Infineon Technologies North America Corp.
    Inventors: George Stojakovic, Matthias Lipinski
  • Patent number: 6815248
    Abstract: A resistive memory device (110) and method of manufacturing thereof comprising a cap layer (140) and hard mask layer (142) disposed over magnetic stacks (114), wherein either the cap layer (140) or hard mask layer (142) comprise WN. A seed layer (136) disposed beneath the magnetic stacks (114) may also be comprised of WN, The use of the material WN improves etch process selectivity during the manufacturing process.
    Type: Grant
    Filed: April 18, 2002
    Date of Patent: November 9, 2004
    Assignee: Infineon Technologies AG
    Inventors: Rainer Leuschner, George Stojakovic, Xian J. Ning
  • Publication number: 20040203242
    Abstract: A method and a system for performing a metal reactive ion etching (RIE) process is disclosed. The metal RIE process comprises at least three steps: a metal RIE step, a stripping step and a wet cleaning step. The metal RIE step and the stripping step are carried out in a main reactive chamber.
    Type: Application
    Filed: April 11, 2003
    Publication date: October 14, 2004
    Inventors: George Stojakovic, Matthias Lipinski
  • Publication number: 20040084400
    Abstract: Patterning metal stack layers of a magnetic switching device to enable a critical lithography level to be made on planar substrate without any topography and enable a second lithography step without topography from a top patterned hardmask, comprising:
    Type: Application
    Filed: October 30, 2002
    Publication date: May 6, 2004
    Inventors: Gregory Costrini, John P. Hummel, George Stojakovic, Kia-Seng Low
  • Publication number: 20030199104
    Abstract: A resistive memory device (110) and method of manufacturing thereof comprising a cap layer (140) and hard mask layer (142) disposed over magnetic stacks (114), wherein either the cap layer (140) or hard mask layer (142) comprise WN. A seed layer (136) disposed beneath the magnetic stacks (114) may also be comprised of WN. The use of the material WN improves etch process selectivity during the manufacturing process.
    Type: Application
    Filed: April 18, 2002
    Publication date: October 23, 2003
    Applicant: Infineon Technologies North America Corp.
    Inventors: Rainer Leuschner, George Stojakovic, Xian J. Ning
  • Publication number: 20030064602
    Abstract: Disclosed is a method of tungsten-based hard mask etching of a wafer, comprising providing a patterned tungsten-based hard mask atop a metal-based surface of said wafer, etching through said pattern with a plasma etch that is selective for said metal-based surface with respect to tungsten, and executing a flash etch selective for tungsten, said etch of at least a minimum duration effective in removing substantially all defects caused by tungsten particulate contaminating said wafer.
    Type: Application
    Filed: September 28, 2001
    Publication date: April 3, 2003
    Inventors: George Stojakovic, Matthias Lipinski
  • Patent number: 6184134
    Abstract: An all dry, low temperature process, for complete removal of organics and inorganic residues after metal etch of a microelectronic device comprising: rinsing a microelectronic device having a metallization layer after metal etch with a solution of ammonium hydroxide and hydrogen peroxide; subjecting the rinsed metallization layer to a low temperature GaSonics cleaning by exposing photoresist residue surface of the metallization layer to a fluorine containing reactive gas to form volatile compounds in the presence of a radio frequency input followed by photoresist stripping in an oxygen plasma at low temperature; subjecting the low temperature GaSonics treated residue surface to a gaseous SO3 strip at low temperature to remove additional residue; and rinsing the SO3 stripped material with de-ionized water to remove any remaining resist and residue.
    Type: Grant
    Filed: February 18, 2000
    Date of Patent: February 6, 2001
    Assignee: Infineon Technologies North America Corp.
    Inventors: Nirmal Chaudhary, Xian J. Ning, George Stojakovic