Abstract: A test circuit for producing a "fail" signal if a clock path driver circuit develops an AC or DC defect. In the simplest embodiment, this test circuit comprises a time delay block for providing a delayed clock signal and its complement, with a delay that exceeds the signal propagation time through the clock receiver and driver; a latch which, in one embodiment, is clocked by the complement of the delayed clock signal to receive the drive signal and to generate pulses which do not overlap in time with the pulses of the delayed clock signal during normal circuit operation; and a gate for detecting such a pulse overlap and for generating an error signal to indicate an AC or DC fault. This circuit effectively detects AC faults at one edge of the clock pulse and one type of DC fault.In a further embodiment of the present invention, this circuit can be combined with a complementary circuit to detect AC faults at both edges of the clock pulse.