Abstract: Disclosed are a method for fabricating a semiconductor device and the associated semiconductor structure. The method includes exposing a photoresist layer disposed on a semiconductor wafer utilizing a grating mask having a plurality of grating lines to produce exposed lines and unexposed lines in the photoresist layer. The method further includes exposing the photoresist layer utilizing a trim mask having a blocking portion situated over a selected one of the unexposed lines. The photoresist layer may be developed after exposing the photoresist layer utilizing the trim mask. A line may then be etched into the semiconductor wafer where the selected one of the unexposed lines was blocked by the blocking portion of the trim mask. The width of the unexposed lines may be controlled by adjusting an exposure time or an exposure power for the photoresist layer while utilizing the grating mask.

Abstract: Disclosed is a heterojunction bipolar transistor (“HBT”) including an intrinsic base in a SiGe layer. The HBT has a raised germanium extrinsic base over the SiGe layer. A base contact is situated over and contacting the raised germanium extrinsic base. An emitter is situated over the intrinsic base, and a collector is situated under the intrinsic base. The raised germanium extrinsic base has a reduced parasitic base-collector capacitance. The raised germanium extrinsic base is situated between a first dielectric layer and a second dielectric layer. Spacers are situated adjacent the second dielectric layer. The first dielectric layer can be a nitride based dielectric, the second dielectric layer can be an oxide based dielectric, and the spacers can be a nitride based dielectric.

Abstract: Disclosed is a method for fabricating a heterojunction bipolar transistor (“HBT”), and the resulting structure. The method includes forming a germanium layer over a SiGe layer, the SiGe layer including an intrinsic base. Thereafter, an emitter sacrificial post and a raised germanium extrinsic base are formed by etching away portions of the germanium layer. Then, a conformal dielectric layer is deposited over the raised germanium extrinsic base. The process continues by removing the emitter sacrificial post and forming an emitter over the intrinsic base within an emitter opening defined by the previous removal of the emitter sacrificial post. The resulting structure has a raised germanium extrinsic base with a reduced parasitic base-collector capacitance.

Abstract: Disclosed is a heterojunction bipolar transistor (“HBT”) including an intrinsic base in a SiGe layer. The HBT has a raised germanium extrinsic base over the SiGe layer. A base contact is situated over and contacting the raised germanium extrinsic base. An emitter is situated over the intrinsic base, and a collector is situated under the intrinsic base. The raised germanium extrinsic base has a reduced parasitic base-collector capacitance. The raised germanium extrinsic base is situated between a first dielectric layer and a second dielectric layer. Spacers are situated adjacent the second dielectric layer. The first dielectric layer can be a nitride based dielectric, the second dielectric layer can be an oxide based dielectric, and the spacers can be a nitride based dielectric.

Abstract: Disclosed is a method for fabricating a heterojunction bipolar transistor (“HBT”), and the resulting structure. The method includes forming a germanium layer over a SiGe layer, the SiGe layer including an intrinsic base. Thereafter, an emitter sacrificial post and a raised germanium extrinsic base are formed by etching away portions of the germanium layer. Then, a conformal dielectric layer is deposited over the raised germanium extrinsic base. The process continues by removing the emitter sacrificial post and forming an emitter over the intrinsic base within an emitter opening defined by the previous removal of the emitter sacrificial post. The resulting structure has a raised germanium extrinsic base with a reduced parasitic base-collector capacitance.

Abstract: Disclosed are a method for fabricating a semiconductor device and the associated semiconductor structure. The method includes exposing a photoresist layer disposed on a semiconductor wafer utilizing a grating mask having a plurality of grating lines to produce exposed lines and unexposed lines in the photoresist layer. The method further includes exposing the photoresist layer utilizing a trim mask having a blocking portion situated over a selected one of the unexposed lines. The photoresist layer may be developed after exposing the photoresist layer utilizing the trim mask. A line may then be etched into the semiconductor wafer where the selected one of the unexposed lines was blocked by the blocking portion of the trim mask. The width of the unexposed lines may be controlled by adjusting an exposure time or an exposure power for the photoresist layer while utilizing the grating mask.

Abstract: In one exemplary embodiment, a resolution enhancement phase shift mask comprises a transparent substrate having a first clear region, a second clear region and a third clear region. An opaque film, such as chrome, is situated over at least a portion of the transparent substrate to define an opaque region. The transparent substrate can be formed of quartz or calcium fluoride, for example. The second and third clear regions have equal thicknesses. However, the first clear region has a thickness different from each of the second and third clear regions. The difference in thickness between the first clear region and the second and third clear regions is calculated to cause a 180 degree phase shift in light passing through the first clear region relative to a phase of light passing through each of the second and third clear regions.

Abstract: A resolution enhancement phase shift mask is disclosed. In one embodiment, a first clear region and second and third clear regions on each side of the first clear region and contiguous to the first clear region are used. All of the clear regions can be made of quartz. The second and third clear regions have an equal thickness. However, both the second and third clear regions are thinner than the first clear region. The difference in thickness between the first clear region and the second and third clear regions is calculated to cause a 180 degree phase shift in light passing through the second and third clear regions relative to light passing through the first clear region. The destructive interference caused at the phase boundaries of the first clear region and the second and third clear regions results in a dark unexposed area on the surface of an underlying photoresist layer; the dark unexposed area having geometry and dimensions corresponding to the geometry and dimensions of the first clear region.

Abstract: A resolution enhancement phase shift mask is disclosed. In one embodiment, a first clear region and second and third clear regions on each side of the first clear region and contiguous to the first clear region are used. All of the clear regions can be made of quartz. The second and third clear regions have an equal thickness. However, both the second and third clear regions are thinner than the first clear region. The difference in thickness between the first clear region and the second and third clear regions is calculated to cause a 180 degree phase shift in light passing through the second and third clear regions relative to light passing through the first clear region. The destructive interference caused at the phase boundaries of the first clear region and the second and third clear regions results in a dark unexposed area on the surface of an underlying photoresist layer; the dark unexposed area having geometry and dimensions corresponding to the geometry and dimensions of the first clear region.