Abstract: Improved power management techniques for computer-readable storage devices are described. In one embodiment, for example, an apparatus may comprise a plurality of logical storage devices and a controller to manage operations of the plurality of logical storage devices, the controller comprising a configuration component to configure a global power consumption threshold defining an overall power consumption budget for the plurality of logical storage devices, a tracking component to maintain a global power consumption tally comprising an estimated total power consumption level for the plurality of logical storage devices, and an arbitration component to resolve an operation request based on the global power consumption threshold and the global power consumption tally. Other embodiments are described and claimed.

Abstract: One or more techniques and/or systems are provided for multicast transport configuration, for multicast transport, and/or for fault policy implementation. In an example, a multicast component may receive a data copy request from an application to copy data to multiple destinations. A scheduler component may create a transport schedule specifying an order with which to facilitate data copy operations across transports, such as heterogeneous transports, to the destinations. A dispatcher component may apply application specified transport modifiers to the data copy operations (e.g., a modification to a quality of service for a transport). The dispatcher component may facilitate the data copy operations and provide operation result information to a policy agent. The policy agent may provide notifications of data copy operation statuses from the operation result information and/or may implement a fault policy (e.g., a retry on a different transport) for a data copy operation that experienced a fault.

Abstract: One or more techniques and/or systems are provided for multicast transport configuration, for multicast transport, and/or for fault policy implementation. In an example, a multicast component may receive a data copy request from an application to copy data to multiple destinations. A scheduler component may create a transport schedule specifying an order with which to facilitate data copy operations across transports, such as heterogeneous transports, to the destinations. A dispatcher component may apply application specified transport modifiers to the data copy operations (e.g., a modification to a quality of service for a transport). The dispatcher component may facilitate the data copy operations and provide operation result information to a policy agent. The policy agent may provide notifications of data copy operation statuses from the operation result information and/or may implement a fault policy (e.g., a retry on a different transport) for a data copy operation that experienced a fault.

Abstract: One or more techniques and/or systems are provided for multicast transport configuration, for multicast transport, and/or for fault policy implementation. In an example, a multicast component may receive a data copy request from an application to copy data to multiple destinations. A scheduler component may create a transport schedule specifying an order with which to facilitate data copy operations across transports, such as heterogeneous transports, to the destinations. A dispatcher component may apply application specified transport modifiers to the data copy operations (e.g., a modification to a quality of service for a transport). The dispatcher component may facilitate the data copy operations and provide operation result information to a policy agent. The policy agent may provide notifications of data copy operation statuses from the operation result information and/or may implement a fault policy (e.g., a retry on a different transport) for a data copy operation that experienced a fault.

Abstract: Examples are disclosed for assessing pass/fail status of non-volatile memory. In some examples, information may be received to indicate a block having memory pages associated with non-volatile memory cells. The information may indicate at least some of the memory pages have bit errors in excess of an error correction code (ECC) ability to correct. For these examples, the block may be selected for read testing. Read testing may include programming the memory pages with a known pattern and waiting a period of time. Following the period of time each memory page may be read and if a resulting pattern read matches the known pattern programmed to each memory page, the memory page passes. The block may be taken offline if the number of passing memory pages is below a pass threshold number. Other examples are described and claimed.

Abstract: In an aspect of the subject matter, a “full” amount of the flash cache (e.g., storage cells) is initially utilized to store data i.e., substantially all of the storage space of the flash cache may be designated to store user data, with the remaining storage space designated to store ECC information (e.g., parity bits) associated with a predefined ECC algorithm utilized to encode the user data. When a bit errors associated with the user data reaches a predefined threshold value, the storage space of the flash cache may transition to store less user data so as to accommodate the space needed to store ECC information associated with a stronger ECC algorithm. The storage space of the flash cache designated to store user data is reduced, while the storage space designated to store ECC information is increased to accommodate the stronger ECC algorithm.

Abstract: A method of operating a storage system is disclosed. The method may include: receiving an I/O request through a network interface involving writing or retrieving a payload data from a storage system; communicating control information of the I/O request to a host processor system without communicating the payload data to the host processor system; receiving a storage access instruction from the host processor system to either retrieve the payload data or to write the payload data; accessing a storage device through a storage interface to execute the storage access instruction involving the payload data; and responding to the I/O request through the network interface without transferring the payload data to a host memory of the host processor system.

Abstract: Improved power management techniques for computer-readable storage devices are described. In one embodiment, for example, an apparatus may comprise a plurality of logical storage devices and a controller to manage operations of the plurality of logical storage devices, the controller comprising a configuration component to configure a global power consumption threshold defining an overall power consumption budget for the plurality of logical storage devices, a tracking component to maintain a global power consumption tally comprising an estimated total power consumption level for the plurality of logical storage devices, and an arbitration component to resolve an operation request based on the global power consumption threshold and the global power consumption tally. Other embodiments are described and claimed.

Abstract: Examples are disclosed for assessing pass/fail status of non-volatile memory. In some examples, information may be received to indicate a block having memory pages associated with non-volatile memory cells. The information may indicate at least some of the memory pages have bit errors in excess of an error correction code (ECC) ability to correct. For these examples, the block may be selected for read testing. Read testing may include programming the memory pages with a known pattern and waiting a period of time. Following the period of time each memory page may be read and if a resulting pattern read matches the known pattern programmed to each memory page, the memory page passes. The block may be taken offline if the number of passing memory pages is below a pass threshold number. Other examples are described and claimed.

Abstract: Described herein are method and apparatus for scheduling access requests for a multi-bank low-latency random read memory (LLRRM) device within a storage system. The LLRRM device comprising a plurality of memory banks, each bank being simultaneously and independently accessible. A queuing layer residing in storage system may allocate a plurality of request-queuing data structures (“queues”), each queue being assigned to a memory bank. The queuing layer may receive access requests for memory banks in the LLRRM device and store each received access request in the queue assigned to the requested memory bank. The queuing layer may then send, to the LLRRM device for processing, an access request from each request-queuing data structure in successive order. As such, requests sent to the LLRRM device will comprise requests that will be applied to each memory bank in successive order as well, thereby reducing access latencies of the LLRRM device.

Abstract: Described herein are method and apparatus for scheduling access requests for a multi-bank low-latency random read memory (LLRRM) device within a storage system. The LLRRM device comprising a plurality of memory banks, each bank being simultaneously and independently accessible. A queuing layer residing in storage system may allocate a plurality of request-queuing data structures (“queues”), each queue being assigned to a memory bank. The queuing layer may receive access requests for memory banks in the LLRRM device and store each received access request in the queue assigned to the requested memory bank. The queuing layer may then send, to the LLRRM device for processing, an access request from each request-queuing data structure in successive order. As such, requests sent to the LLRRM device will comprise requests that will be applied to each memory bank in successive order as well, thereby reducing access latencies of the LLRRM device.

Abstract: Method and apparatus for scheduling access requests for a multi-bank low-latency random read memory (LLRRM) device within a storage system. The LLRRM device comprising a plurality of memory banks, each bank being simultaneously and independently accessible. A queuing layer residing in storage system may allocate a plurality of request-queuing data structures (“queues”), each queue being assigned to a memory bank. The queuing layer may receive access requests for memory banks in the LLRRM device and store each received access request in the queue assigned to the requested memory bank. The queuing layer may then send, to the LLRRM device for processing, an access request from each request-queuing data structure in successive order. As such, requests sent to the LLRRM device will comprise requests that will be applied to each memory bank in successive order as well, thereby reducing access latencies of the LLRRM device.

Abstract: Described herein are method and apparatus for storing data to a low-latency random read memory (LLRRM) device using non-aligned data striping, the LLRRM device being implemented on a storage system. The LLRRM device may comprise a bank comprising a plurality of memory chips, each chip being simultaneously accessible for storing data on a plurality of erase-units (EUs). A storage operating system may maintain, for each chip, a reserve data structure listing reserve EUs and a remapping data structure for tracking remappings between defective EUs to reserve EUs in the chip. A defective EU in a chip may be mapped to a reserve EU from the reserve data structure. Upon receiving a data block to be stored to the LLRRM device at the defective EU, the storage operating system may stripe the received data block across a plurality of chips in a non-aligned manner using the remapped reserve EU.

Abstract: A method of managing power states of memory modules while performing memory access operations is disclosed. Memory modules are in a power saving state until an access operation involving the module is to be performed. The module is placed in an operational mode, then the access operation is performed, then the module is returned to the power saving state. Apparatus and systems using the method are also disclosed and claimed.

Abstract: Described herein are method and apparatus for storing data to a low-latency random read memory (LLRRM) device using non-aligned data striping, the LLRRM device being implemented on a storage system. The LLRRM device may comprise a bank comprising a plurality of memory chips, each chip being simultaneously accessible for storing data on a plurality of erase-units (EUs). A storage operating system may maintain, for each chip, a reserve data structure listing reserve EUs and a remapping data structure for tracking remappings between defective EUs to reserve EUs in the chip. A defective EU in a chip may be mapped to a reserve EU from the reserve data structure. Upon receiving a data block to be stored to the LLRRM device at the defective EU, the storage operating system may stripe the received data block across a plurality of chips in a non-aligned manner using the remapped reserve EU.

Abstract: Described herein are method and apparatus for storing data to a low-latency random read memory (LLRRM) device using non-aligned data striping, the LLRRM device being implemented on a storage system. The LLRRM device may comprise a bank comprising a plurality of memory chips, each chip being simultaneously accessible for storing data on a plurality of erase-units (EUs). A storage operating system may maintain, for each chip, a reserve data structure listing reserve EUs and a remapping data structure for tracking remappings between defective EUs to reserve EUs in the chip. A defective EU in a chip may be mapped to a reserve EU from the reserve data structure. Upon receiving a data block to be stored to the LLRRM device at the defective EU, the storage operating system may stripe the received data block across a plurality of chips in a non-aligned manner using the remapped reserve EU.

Abstract: A system and method for protecting memory during system initialization is provided. A complex programmable logic device (CPLD) is operatively interconnected with a multiplexer to enable control of a memory to be switched between a memory controller and the CPLD in response to error conditions. If an error condition is identified, the CPLD assumes control of the memory and activates a battery subsystem to provide memory refreshes until system re-initialization. Upon system bring-up, interactions between the BIOS and CPLD assure that protected memory is fully recovered by the system. The contents of memory will remain protected from any further faults that may occur during the bring-up sequence.

Abstract: The battery apparatus introduced here provides a tool for reliably measuring the run time to empty of a battery used in a network storage server for protection of data during a failure mode. The battery run time to empty can be determined by a management controller based on battery information generated by a controller and received at the management controller. The information received at the management controller includes run time to empty, voltage, current and current battery capacity.

Abstract: A system and method protects the contents of memory during error conditions. An illustrative storage system includes a complex programmable logic device (CPLD) that interfaces with a memory controller and a basic input output system (BIOS) for ensuring that the system memory is maintained in a self refresh state in the event of an error condition. The memory controller is configured to, in response to receiving a signal from the CPLD, cause the memory to enter the self refresh state where it is maintained by a battery subsystem (or alternate power sources). Accordingly, data contained within the memory may be replayed to persistent storage upon correction of the error condition via, for example, a system re-initialization.

Abstract: A method of managing power states of memory modules while performing memory access operations is disclosed. Memory modules are in a power saving state until an access operation involving the module is to be performed. The module is placed in an operational mode, then the access operation is performed, then the module is returned to the power saving state. Apparatus and systems using the method are also disclosed and claimed.