Abstract: A system for data pulse transmission through a single-wire, water-return cable payed out from a coil in an open pack to any selected length over a predetermined wide range (e.g., 4K to 16K feet) employing a toroidal core around the cable near the pack and a multiturn primary winding on the core. The single-wire cable constitutes a single turn secondary winding terminated at the receiver end by a resistor and coupled to the water (circuit ground) at the transmitting end by stray capacitance between the cable remaining in the pack and the surrounding water. The receiver employs an equalizing network to compensate for the amplitude-frequency characteristic of the cable of nominal length within the predetermined range resulting in only slight over-compensation for a shorter cable length and slight under-compensation for a longer cable length.

Abstract: A low power digital memory comprised of a matrix of memory cells suitable for fabrication by large scale integrated circuit techniques. Each memory cell is comprised of field effect transistors, preferably metal oxide semiconductors. A plurality of cells are fabricated on a single monolithic chip and are interconnected for coincident signal addressing. Power is conserved by periodically pulsing load transistors rather than biasing them continuously on.