Patents by Inventor George Vakanas

George Vakanas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200098727
    Abstract: A wire-bond memory die is coupled to a system-on-chip processor where the processor is flip-chip mounted on a semiconductor package substrate, and the wire-bond memory die is also flip-chip configured through a redistribution layer that pins out to a series of pillars that contact the semiconductor package substrate. The wire-bond memory die is stacked on the processor and the redistribution layer overhangs the processor to contact the series of pillars.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Inventors: Debendra Mallik, Robert L. Sankman, Sanka Ganesan, George Vakanas, Omkar Karhade, Sri Chaitra Jyotsna Chavali, Zhaozhi George Li, Holly A. Sawyer
  • Publication number: 20200043894
    Abstract: Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a package substrate, and a first die coupled to the package substrate. In an embodiment, a cavity is formed through the package substrate. In an embodiment, the cavity is within a footprint of the first die. In an embodiment, the electronics package further comprises a thermal stack in the cavity. In an embodiment, the thermal stack contacts the first die.
    Type: Application
    Filed: July 31, 2018
    Publication date: February 6, 2020
    Inventors: George VAKANAS, Aastha UPPAL, Shereen ELHALAWATY, Aaron MCCANN, Edvin CETEGEN, Tannaz HARIRCHIAN, Saikumar JAYARAMAN
  • Patent number: 10066303
    Abstract: The invention relates to a substrate having at least one main surface comprising at least one non-noble metallic bonding landing pad covered by a capping layer thereby shielding the non-noble metallic bonding landing pad from the environment. This capping layer comprises an alloy, the alloy being NiB or CoB and containing an atomic concentration percentage of boron in the range of 10% to 50%.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: September 4, 2018
    Assignees: IMEC VZW, GLOBALFOUNDRIES INC.
    Inventors: Eric Beyne, Joeri De Vos, Jaber Derakhshandeh, Luke England, George Vakanas
  • Publication number: 20150247244
    Abstract: The invention relates to a substrate having at least one main surface comprising at least one non-noble metallic bonding landing pad covered by a capping layer thereby shielding the non-noble metallic bonding landing pad from the environment. This capping layer comprises an alloy, the alloy being NiB or CoB and containing an atomic concentration percentage of boron in the range of 10% to 50%.
    Type: Application
    Filed: February 27, 2015
    Publication date: September 3, 2015
    Inventors: Eric Beyne, Joeri De Vos, Jaber Derakhshandeh, Luke England, George Vakanas
  • Patent number: 8426250
    Abstract: The present invention discloses an apparatus including: a laser beam directed at a wafer held by a chuck mounted on a stage inside a process chamber; a focusing mechanism for the laser beam; a steering mechanism for the laser beam; an optical scanning mechanism for the laser beam; a mechanical scanning system for the stage; an etch chemical induced by the laser beam to etch the wafer and form volatile byproducts; a gas feed line to dispense the etch chemical towards the wafer; and a gas exhaust line to remove any excess of the etch chemical and the volatile byproducts.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: April 23, 2013
    Assignee: Intel Corporation
    Inventors: George Vakanas, George Chen, Yuval Greenzweig, Eric Li, Sergei Voronov
  • Patent number: 8163598
    Abstract: In one or more embodiments, a method comprising applying thermo compression to a package assembly including a lid, a die, and a package substrate to assemble the package assembly is disclosed. The method may include assembling the package assembly without coupling a biasing mechanism to the lid. Heat may be applied to a bond head coupled with a pick and place tool. Heat may be applied to a bond stage coupled to a carrier for holding the package assembly during processing. An adhesive applied to the lid or package substrate may be allowed to at least partially cure. The method may further include, in an oven, reflowing a thermal interface material (TIM) coupled to the lid and the die, curing the TIM, and/or curing the adhesive, without using clips.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: April 24, 2012
    Assignee: Intel Corporation
    Inventors: George Kostiew, Raj Bahadur, James Mellody, George Vakanas, Leonel Arana
  • Publication number: 20110129963
    Abstract: In one or more embodiments, a method comprising applying thermo compression to a package assembly including a lid, a die, and a package substrate to assemble the package assembly is disclosed. The method may include assembling the package assembly without coupling a biasing mechanism to the lid. Heat may be applied to a bond head coupled with a pick and place tool. Heat may be applied to a bond stage coupled to a carrier for holding the package assembly during processing. An adhesive applied to the lid or package substrate may be allowed to at least partially cure. The method may further include, in an oven, reflowing a thermal interface material (TIM) coupled to the lid and the die, curing the TIM, and/or curing the adhesive, without using clips.
    Type: Application
    Filed: January 14, 2011
    Publication date: June 2, 2011
    Inventors: George Kostiew, Raj Bahadur, James Mellody, George Vakanas, Leonel Arana
  • Patent number: 7892883
    Abstract: In one or more embodiments, a method comprising applying thermo compression to a package assembly including a lid, a die, and a package substrate to assemble the package assembly is disclosed. The method may include assembling the package assembly without coupling a biasing mechanism to the lid. Heat may be applied to a bond head coupled with a pick and place tool. Heat may be applied to a bond stage coupled to a carrier for holding the package assembly during processing. An adhesive applied to the lid or package substrate may be allowed to at least partially cure. The method may further include, in an oven, reflowing a thermal interface material (TIM) coupled to the lid and the die, curing the TIM, and/or curing the adhesive, without using clips.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: February 22, 2011
    Assignee: Intel Corporation
    Inventors: George Kostiew, Raj Bahadur, James Mellody, George Vakanas, Leonel Arana
  • Publication number: 20100129984
    Abstract: The present invention discloses an apparatus including: a laser beam directed at a wafer held by a chuck in a process chamber; a focusing mechanism for the laser beam; a steering mechanism for the laser beam; an optical scanning mechanism for the laser beam; a mechanical scanning system for the chuck; an etch chemical induced by the laser beam to etch the wafer and form volatile byproducts; a gas feed line to dispense the etch chemical towards the wafer; and a gas exhaust line to remove any excess of the etch chemical and the volatile byproducts.
    Type: Application
    Filed: November 26, 2008
    Publication date: May 27, 2010
    Inventors: George Vakanas, George Chen, Yuval Greenzweig, Eric Li, Sergei Voronov
  • Publication number: 20100099238
    Abstract: The present invention discloses an apparatus including: a laser beam directed at a wafer held by a chuck mounted on a stage inside a process chamber; a focusing mechanism for the laser beam; a steering mechanism for the laser beam; an optical scanning mechanism for the laser beam; a mechanical scanning system for the stage; an etch chemical induced by the laser beam to etch the wafer and form volatile byproducts; a gas feed line to dispense the etch chemical towards the wafer; and a gas exhaust line to remove any excess of the etch chemical and the volatile byproducts.
    Type: Application
    Filed: October 22, 2008
    Publication date: April 22, 2010
    Inventors: George Vakanas, George Chen, Yuval Greenzweig, Eric Li, Sergei Voronov
  • Publication number: 20090298235
    Abstract: In one or more embodiments, a method comprising applying thermo compression to a package assembly including a lid, a die, and a package substrate to assemble the package assembly is disclosed. The method may include assembling the package assembly without coupling a biasing mechanism to the lid. Heat may be applied to a bond head coupled with a pick and place tool. Heat may be applied to a bond stage coupled to a carrier for holding the package assembly during processing. An adhesive applied to the lid or package substrate may be allowed to at least partially cure. The method may further include, in an oven, reflowing a thermal interface material (TIM) coupled to the lid and the die, curing the TIM, and/or curing the adhesive, without using clips.
    Type: Application
    Filed: May 30, 2008
    Publication date: December 3, 2009
    Inventors: George Kostiew, Raj Bahadur, James Mellody, George Vakanas, Leonel Arana
  • Publication number: 20050090034
    Abstract: A method and apparatus for rapid prototyping and fabrication of passivated microfluidic structures is disclosed. The method and apparatus may be used to fabricate and passivate the channel in one system.
    Type: Application
    Filed: October 28, 2004
    Publication date: April 28, 2005
    Inventors: Paul Winer, George Vakanas